Loading boards/riscv/opentitan_earlgrey/doc/index.rst +4 −1 Original line number Diff line number Diff line Loading @@ -20,7 +20,8 @@ Hardware - 32 x GPIO - 4 x UART - 3 x I2C - 2 x SPI - 2 x SPI host - 1 x SPI device - Various security peripherals Detailed specification is on the `OpenTitan Earl Grey Chip Datasheet`_. Loading @@ -40,6 +41,8 @@ the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool. +-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling | +-----------+------------+-------------------------------------+ | SPI | on-chip | SPI host | +-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. Loading boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts +8 −0 Original line number Diff line number Diff line Loading @@ -29,3 +29,11 @@ &mtimer { status = "okay"; }; &spi0 { status = "okay"; }; &spi1 { status = "okay"; }; dts/riscv/lowrisc/opentitan_earlgrey.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,24 @@ compatible = "lowrisc,opentitan-uart"; status = "disabled"; }; spi0: spi@40300000 { compatible = "lowrisc,opentitan-spi"; status = "disabled"; reg = <0x40300000 0x100>; clock-frequency = <96000000>; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@40310000 { compatible = "lowrisc,opentitan-spi"; status = "disabled"; reg = <0x40310000 0x100>; clock-frequency = <48000000>; #address-cells = <1>; #size-cells = <0>; }; }; }; Loading
boards/riscv/opentitan_earlgrey/doc/index.rst +4 −1 Original line number Diff line number Diff line Loading @@ -20,7 +20,8 @@ Hardware - 32 x GPIO - 4 x UART - 3 x I2C - 2 x SPI - 2 x SPI host - 1 x SPI device - Various security peripherals Detailed specification is on the `OpenTitan Earl Grey Chip Datasheet`_. Loading @@ -40,6 +41,8 @@ the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool. +-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling | +-----------+------------+-------------------------------------+ | SPI | on-chip | SPI host | +-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. Loading
boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts +8 −0 Original line number Diff line number Diff line Loading @@ -29,3 +29,11 @@ &mtimer { status = "okay"; }; &spi0 { status = "okay"; }; &spi1 { status = "okay"; };
dts/riscv/lowrisc/opentitan_earlgrey.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,24 @@ compatible = "lowrisc,opentitan-uart"; status = "disabled"; }; spi0: spi@40300000 { compatible = "lowrisc,opentitan-spi"; status = "disabled"; reg = <0x40300000 0x100>; clock-frequency = <96000000>; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@40310000 { compatible = "lowrisc,opentitan-spi"; status = "disabled"; reg = <0x40310000 0x100>; clock-frequency = <48000000>; #address-cells = <1>; #size-cells = <0>; }; }; };
Shawn Nematbakhsh <shawn@rivosinc.com>Shawn Nematbakhsh <shawn@rivosinc.com>