Commit b15ce880 authored by Ioannis Glaropoulos's avatar Ioannis Glaropoulos Committed by Carles Cufi
Browse files

dts: arm: nordic: nRF5340 Application MCU DTS structure 



- Adding nRF5340 Application (CPU APP) common (Secure/Non-Secure)
peripheral DTS representation.
- Adding nrf5340 Application (CPU APP) default (Secure)
 .dtsi headers
- Adding nrf5340 Application (CPU APP) Non-Secure
 .dtsi headers
- Added nRF53 flash controller binding

Signed-off-by: default avatarIoannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
parent 92625d71

dts/arm/nordic/nrf5340_cpuapp.dtsi

0 → 100644
+110 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <arm/armv8-m.dtsi>

#include <dt-bindings/i2c/i2c.h>

#include <dt-bindings/gpio/gpio.h>



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-m33f";

			reg = <0>;

			#address-cells = <1>;

			#size-cells = <1>;



			mpu: mpu@e000ed90 {

				compatible = "arm,armv8m-mpu";

				reg = <0xe000ed90 0x40>;

				arm,num-mpu-regions = <16>;

			};

		};

	};



	aliases {

		flash-controller = &flash_controller;

		rtc-0 = &rtc0;

		rtc-1 = &rtc1;

		uart-0 = &uart0;

		uart-1 = &uart1;

		adc-0 = &adc;

		egu-0 = &egu0;

		egu-1 = &egu1;

		egu-2 = &egu2;

		egu-3 = &egu3;

		egu-4 = &egu4;

		egu-5 = &egu5;

		gpio-0 = &gpio0;

		gpio-1 = &gpio1;

		gpiote-0 = &gpiote;

		i2c-0 = &i2c0;

		i2c-1 = &i2c1;

		pdm-0 = &pdm0;

		spi-0 = &spi0;

		spi-1 = &spi1;

		spi-2 = &spi2;

		pwm-0 = &pwm0;

		pwm-1 = &pwm1;

		pwm-2 = &pwm2;

		wdt-0 = &wdt;

		timer-0 = &timer0;

		timer-1 = &timer1;

		timer-2 = &timer2;

	};



	soc {

		sram0: memory@20000000 {

			compatible = "mmio-sram";

		};



		peripheral@50000000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x50000000 0x10000000>;



			/* Common nRF5340 Application MCU

			 * peripheral description

			 */

			#include "nrf5340_cpuapp_common.dtsi"

		};



		/* Additional Secure peripherals */

		gpiote: gpiote@5000d000 {

			compatible = "nordic,nrf-gpiote";

			reg = <0x5000d000 0x1000>;

			interrupts = <13 5>;

			status = "disabled";

			label = "GPIOTE_0";

		};



		spu: spu@50003000 {

			compatible = "nordic,nrf-spu";

			reg = <0x50003000 0x1000>;

			interrupts = <3 1>;

			status = "okay";

		};



		ficr: ficr@ff0000 {

			compatible = "nordic,nrf-ficr";

			reg = <0xff0000 0x1000>;

			status = "okay";

		};



		uicr: uicr@ff8000 {

			compatible = "nordic,nrf-uicr";

			reg = <0xff8000 0x1000>;

			status = "okay";

		};

	};

};



&nvic {

	arm,num-irq-priority-bits = <3>;

};

dts/arm/nordic/nrf5340_cpuapp_common.dtsi

0 → 100644
+327 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: Apache-2.0

 */



flash_controller: flash-controller@39000 {

	compatible = "nordic,nrf53-flash-controller";

	reg = <0x39000 0x1000>;



	#address-cells = <1>;

	#size-cells = <1>;



	label = "NRF_FLASH_DRV_NAME";



	flash0: flash@0 {

		compatible = "soc-nv-flash";

		label = "NRF_FLASH";

		erase-block-size = <4096>;

		write-block-size = <4>;

	};

};



adc: adc@e000 {

	compatible = "nordic,nrf-saadc";

	reg = <0xe000 0x1000>;

	interrupts = <14 1>;

	status = "disabled";

	label = "ADC_0";

	#io-channel-cells = <1>;

};



dppic: dppic@17000 {

	compatible = "nordic,nrf-dppic";

	reg = <0x17000 0x1000>;

	status = "okay";

	label = "DPPIC";

};



egu0: egu@1b000 {

	compatible = "nordic,nrf-egu";

	reg = <0x1b000 0x1000>;

	interrupts = <27 1>;

	status = "okay";

};



egu1: egu@1c000 {

	compatible = "nordic,nrf-egu";

	reg = <0x1c000 0x1000>;

	interrupts = <28 1>;

	status = "okay";

};



egu2: egu@1d000 {

	compatible = "nordic,nrf-egu";

	reg = <0x1d000 0x1000>;

	interrupts = <29 1>;

	status = "okay";

};



egu3: egu@1e000 {

	compatible = "nordic,nrf-egu";

	reg = <0x1e000 0x1000>;

	interrupts = <30 1>;

	status = "okay";

};



egu4: egu@1f000 {

	compatible = "nordic,nrf-egu";

	reg = <0x1f000 0x1000>;

	interrupts = <31 1>;

	status = "okay";

};



egu5: egu@20000 {

	compatible = "nordic,nrf-egu";

	reg = <0x20000 0x1000>;

	interrupts = <32 1>;

	status = "okay";

};



i2s0: i2s@28000 {

	compatible = "nordic,nrf-i2s";

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0x28000 0x1000>;

	interrupts = <40 1>;

	status = "disabled";

	label = "I2S_0";

};



ipc: ipc@2a000 {

	compatible = "nordic,nrf-ipc";

	reg = <0x2a000 0x1000>;

	interrupts = <42 1>;

	status = "okay";

	label = "IPC";

};



kmu: kmu@39000 {

	compatible = "nordic,nrf-kmu";

	reg = <0x39000 0x1000>;

	interrupts = <57 1>;

	status = "okay";

};



pdm0: pdm@26000 {

	compatible = "nordic,nrf-pdm";

	reg = <0x26000 0x1000>;

	interrupts = <38 1>;

	status = "disabled";

	label = "PDM_0";

};



regulators: regulator@4000 {

	compatible = "nordic,nrf-regulators";

	reg = <0x4000 0x1000>;

	status = "okay";

};



vmc: vmc@81000 {

	compatible = "nordic,nrf-vmc";

	reg = <0x81000 0x1000>;

	status = "okay";

};



uart0: uart@8000 {

	compatible = "nordic,nrf-uarte";

	reg = <0x8000 0x1000>;

	interrupts = <8 1>;

	status = "disabled";

	label = "UART_0";

};



uart1: uart@9000 {

	compatible = "nordic,nrf-uarte";

	reg = <0x9000 0x1000>;

	interrupts = <9 1>;

	status = "disabled";

	label = "UART_1";

};



i2c0: i2c@8000 {

	/*

	 * This i2c node can be either TWIM or TWIS, for the user to pick:

	 * compatible = "nordic,nrf-twim" or

	 *              "nordic,nrf-twis".

	 */

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0x8000 0x1000>;

	clock-frequency = <I2C_BITRATE_STANDARD>;

	interrupts = <8 1>;

	status = "disabled";

	label = "I2C_0";

};



i2c1: i2c@9000 {

	/*

	 * This i2c node can be TWIM or TWIS,

	 * for the user to pick:

	 * compatible = "nordic,nrf-twim" or

	 *              "nordic,nrf-twis".

	 */

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0x9000 0x1000>;

	clock-frequency = <I2C_BITRATE_STANDARD>;

	interrupts = <9 1>;

	status = "disabled";

	label = "I2C_1";

};



spi0: spi@8000 {

	/*

	 * This spi node can be either SPIM or SPIS,

	 * for the user to pick:

	 * compatible = "nordic,nrf-spim" or

	 *              "nordic,nrf-spis".

	 */

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0x8000 0x1000>;

	interrupts = <8 1>;

	status = "disabled";

	label = "SPI_0";

};



spi1: spi@9000 {

	/*

	 * This spi node can be either SPIM or SPIS,

	 * for the user to pick:

	 * compatible = "nordic,nrf-spim" or

	 *              "nordic,nrf-spis".

	 */

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0x9000 0x1000>;

	interrupts = <9 1>;

	status = "disabled";

	label = "SPI_1";

};



spi2: spi@a000 {

	compatible = "nordic,nrf-spim";

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0xa000 0x1000>;

	interrupts = <10 1>;

	status = "disabled";

	label = "SPI_2";

};



pwm0: pwm@21000 {

	compatible = "nordic,nrf-pwm";

	reg = <0x21000 0x1000>;

	interrupts = <33 1>;

	status = "disabled";

	label = "PWM_0";

	#pwm-cells = <1>;

};



pwm1: pwm@22000 {

	compatible = "nordic,nrf-pwm";

	reg = <0x22000 0x1000>;

	interrupts = <34 1>;

	status = "disabled";

	label = "PWM_1";

	#pwm-cells = <1>;

};



pwm2: pwm@23000 {

	compatible = "nordic,nrf-pwm";

	reg = <0x23000 0x1000>;

	interrupts = <35 1>;

	status = "disabled";

	label = "PWM_2";

	#pwm-cells = <1>;

};



gpio0: gpio@842500 {

	compatible = "nordic,nrf-gpio";

	gpio-controller;

	reg = <0x842500 0x300>;

	#gpio-cells = <2>;

	label = "GPIO_0";

	status = "disabled";

};



gpio1: gpio@842800 {

	compatible = "nordic,nrf-gpio";

	gpio-controller;

	reg = <0x842800 0x300>;

	#gpio-cells = <2>;

	label = "GPIO_1";

	status = "disabled";

};



rtc0: rtc@14000 {

	compatible = "nordic,nrf-rtc";

	reg = <0x14000 0x1000>;

	interrupts = <20 1>;

	status = "okay";

	clock-frequency = <32768>;

	prescaler = <1>;

	label = "RTC_0";

};



rtc1: rtc@15000 {

	compatible = "nordic,nrf-rtc";

	reg = <0x15000 0x1000>;

	interrupts = <21 1>;

	status = "okay";

	clock-frequency = <32768>;

	prescaler = <1>;

	label = "RTC_1";

};



clock: clock@5000 {

	compatible = "nordic,nrf-clock";

	reg = <0x5000 0x1000>;

	interrupts = <5 1>;

	status = "okay";

	label = "CLOCK";

};



power: power@5000 {

	compatible = "nordic,nrf-power";

	reg = <0x5000 0x1000>;

	interrupts = <5 1>;

	status = "okay";

};



wdt: watchdog@18000 {

	compatible = "nordic,nrf-watchdog";

	reg = <0x18000 0x1000>;

	interrupts = <24 1>;

	status = "okay";

	label = "WDT";

};



timer0: timer@f000 {

	compatible = "nordic,nrf-timer";

	status = "disabled";

	reg = <0xf000 0x1000>;

	interrupts = <15 1>;

	prescaler = <0>;

	label = "TIMER_0";

};



timer1: timer@10000 {

	compatible = "nordic,nrf-timer";

	status = "disabled";

	reg = <0x10000 0x1000>;

	interrupts = <16 1>;

	prescaler = <0>;

	label = "TIMER_1";

};



timer2: timer@11000 {

	compatible = "nordic,nrf-timer";

	status = "disabled";

	reg = <0x11000 0x1000>;

	interrupts = <17 1>;

	prescaler = <0>;

	label = "TIMER_2";

};

dts/arm/nordic/nrf5340_cpuapp_qkaa.dtsi

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <mem.h>

#include <nordic/nrf5340_cpuapp.dtsi>



&flash0 {

	reg = <0x00000000 DT_SIZE_K(1024)>;

};



&sram0 {

	reg = <0x20000000 DT_SIZE_K(512)>;

};



/ {

	soc {

		compatible = "nordic,nRF5340-CPU0-QKAA", "nordic,nRF5340-CPU0", "nordic,nRF53", "simple-bus";

	};

};

dts/arm/nordic/nrf5340_cpuappns.dtsi

0 → 100644
+87 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: Apache-2.0

 */



/* .dtsi header for nRF5340 CPUAPP (Application MCU), Non-Secure domain */



#include <arm/armv8-m.dtsi>

#include <dt-bindings/i2c/i2c.h>

#include <dt-bindings/gpio/gpio.h>



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-m33f";

			reg = <0>;

			#address-cells = <1>;

			#size-cells = <1>;



			mpu: mpu@e000ed90 {

				compatible = "arm,armv8m-mpu";

				reg = <0xe000ed90 0x40>;

				arm,num-mpu-regions = <16>;

			};

		};

	};



	aliases {

		flash-controller = &flash_controller;

		rtc-0 = &rtc0;

		rtc-1 = &rtc1;

		uart-0 = &uart0;

		uart-1 = &uart1;

		adc-0 = &adc;

		gpio-0 = &gpio0;

		gpio-1 = &gpio1;

		gpiote-0 = &gpiote;

		i2c-0 = &i2c0;

		i2c-1 = &i2c1;

		spi-0 = &spi0;

		spi-1 = &spi1;

		spi-2 = &spi2;

		pwm-0 = &pwm0;

		pwm-1 = &pwm1;

		pwm-2 = &pwm2;

		wdt-0 = &wdt;

		timer-0 = &timer0;

		timer-1 = &timer1;

		timer-2 = &timer2;

	};



	soc {

		sram0: memory@20000000 {

			device_type = "memory";

			compatible = "mmio-sram";

		};



		peripheral@40000000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x40000000 0x10000000>;



			/* Common nRF5340 Application MCU

			 * peripheral description

			 */

			#include "nrf5340_cpuapp_common.dtsi"

		};



		/* Additional Non-Secure peripherals */

		gpiote: gpiote@4002f000 {

			compatible = "nordic,nrf-gpiote";

			reg = <0x4002f000 0x1000>;

			interrupts = <47 5>;

			status = "disabled";

			label = "GPIOTE_1";

		};

	};

};



&nvic {

	arm,num-irq-priority-bits = <3>;

};

dts/arm/nordic/nrf5340_cpuappns_qkaa.dtsi

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019 Nordic Semiconductor ASA

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <mem.h>

#include <nordic/nrf5340_cpuappns.dtsi>



&flash0 {

	reg = <0x00000000 DT_SIZE_K(1024)>;

};



&sram0 {

	reg = <0x20000000 DT_SIZE_K(512)>;

};



/ {

	soc {

		compatible = "nordic,nRF5340-CPU0-QKAA", "nordic,nRF5340-CPU0", "nordic,nRF53", "simple-bus";

	};

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE