drivers: fpga: fix waveform for iCE40 configuration in SPI mode

The datasheet of the iCE40 specifies that there should be a leading and
trailing clocks phase during its configuration with SPI. Due to the
limitations of the SPI interface, and probably also due to a lock of
support for such a feature for instance in the STM32 SPI peripheral,
this is achieved with additional SPI transfers before and after the
actual image. Unfortunately, this by default also affects the slave
select GPIO, which has to stay high during these phases.
This fixes this behaviour via not passing the slave select GPIO
to the SPI driver and manipulating this GPIO manually.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>