boards: add support for HiFive Unleashed

# Copyright (c) 2021 Katsuhiro Suzuki

# SPDX-License-Identifier: Apache-2.0

config BOARD_HIFIVE_UNLEASHED

	bool "HiFive Unleashed target"

	depends on SOC_RISCV_SIFIVE_FU540

# Copyright (c) 2021 Katsuhiro Suzuki

# SPDX-License-Identifier: Apache-2.0

if BOARD_HIFIVE_UNLEASHED

config BOARD

	default "hifive_unleashed"

config SYS_CLOCK_TICKS_PER_SEC

	default 1000

config SYS_CLOCK_HW_CYCLES_PER_SEC

	default 1000000

config SPI_SIFIVE

	default y

	depends on SPI

config UART_SIFIVE

	default y

	depends on SERIAL

endif

# SPDX-License-Identifier: Apache-2.0

set(OPENOCD_USE_LOAD_IMAGE NO)

board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_hifive_unleashed.cfg")

include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

.. _hifive_unleashed:

SiFive HiFive Unleashed

#######################

Overview

********

The HiFive Unleashed is a development board with a SiFive FU540-C000

multi-core 64bit RISC-V SoC.

Programming and debugging

*************************

Building

========

Applications for the ``hifive_unleashed`` board configuration can be built as

usual (see :ref:`build_an_application`) using the corresponding board name:

.. zephyr-app-commands::

   :board: hifive_unleashed

   :goals: build

Flashing

========

Current version has not yet supported flashing binary to onboard Flash ROM.

This board has USB-JTAG interface and this can be used with OpenOCD.

Load applications on DDR and run as follows:

.. code-block:: console

   openocd -c 'bindto 0.0.0.0' \

           -f boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg

   riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf

   (gdb) target remote :3333

   (gdb) c

Debugging

=========

Refer to the detailed overview about :ref:`application_debugging`.

/*

 * Copyright (c) 2021 Katsuhiro Suzuki

 *

 * SPDX-License-Identifier: Apache-2.0

 */

/dts-v1/;

#include <riscv64-fu540.dtsi>

/ {

	chosen {

		zephyr,console = &uart0;

		zephyr,shell-uart = &uart0;

		zephyr,sram = &ram0;

	};

	ram0: ram0@80000000 {

		compatible = "memory";

		reg = <0x80000000 0xf0000000>;

		reg-names = "mem";

	};

};

&uart0 {

	status = "okay";

	current-speed = <115200>;

	clock-frequency = <500000000>;

};

&spi0 {

	status = "okay";

	clock-frequency = <500000000>;

	reg = <0x10040000 0x1000 0x20000000 0x2000000>;

	flash0: flash@0 {

		compatible = "issi,is25wp256d", "jedec,spi-nor";

		size = <33554432>;

		label = "FLASH0";

		jedec-id = [96 60 18];

		reg = <0>;

		spi-max-frequency = <133000000>;

	};

};

&spi1 {

	status = "okay";

	clock-frequency = <500000000>;

};

&spi2 {

	status = "okay";

	clock-frequency = <500000000>;

};