drivers: clock_control: stm32h7: Fix frequency calculation overflow

STM32h7 pllout frequency calculation overflows. In the
worst case pllsrc_freq can be 50Mhz and plln_mul 512 which will cause
an overflow of the intermediate result which leads to wrong frequency
returned. As no intermediate result can be bigger than 960MHz only the
order of operations is changed.

Signed-off-by: Benjamin Bigler <benjamin.bigler@securiton.ch>