drivers: clock_control: stm32h7 fix high frequency setting

Fixes #27212 by setting the AHB/APBx dividers
prior to configuring the PLL as clock source.

Prevents going over the limits of APBx clocks when
choosing the PLL as system clock source for
high frequencies (close to 480MHz)

Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>