arch: x86: update with new acpica lib interface (a68204d8) · Commits · Wenxi XU / zephyr

arch/x86/Kconfig

+2 −8

Original line number	Diff line number	Diff line
		@@ -227,22 +227,16 @@ choice
		Reboot via the RST_CNT register, going back to BIOS.
		endchoice

		config X86_ACPI
		bool "ACPI (Advanced Configuration and Power Interface) support"
		depends on X86_PC_COMPATIBLE
		help
		Allow retrieval of platform configuration at runtime.

		config PCIE_MMIO_CFG
		bool "Use MMIO PCI configuration space access"
		select X86_ACPI
		select ACPI
		help
		Selects the use of the memory-mapped PCI Express Extended
		Configuration Space instead of the traditional 0xCF8/0xCFC
		IO Port registers.

		config KERNEL_VM_SIZE
		default 0x40000000 if X86_ACPI
		default 0x40000000 if ACPI

		config X86_PC_COMPATIBLE
		bool

+1 −1

Original line number	Diff line number	Diff line
		@@ -15,7 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_PCIE pcie.c)
		zephyr_library_sources_ifdef(CONFIG_REBOOT_RST_CNT reboot_rst_cnt.c)
		zephyr_library_sources_ifdef(CONFIG_MULTIBOOT_INFO multiboot.c)
		zephyr_library_sources_ifdef(CONFIG_X86_EFI efi.c)
		zephyr_library_sources_ifdef(CONFIG_X86_ACPI acpi.c)
		zephyr_library_sources_ifdef(CONFIG_ACPI legacy_bios.c)
		zephyr_library_sources_ifdef(CONFIG_X86_MMU x86_mmu.c)
		zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.c)
		zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)

+6 −7

Original line number	Diff line number	Diff line
		@@ -11,7 +11,7 @@
		#include <zephyr/arch/x86/multiboot.h>
		#include <x86_mmu.h>
		#include <zephyr/drivers/interrupt_controller/loapic.h>
		#include <zephyr/arch/x86/acpi.h>
		#include <zephyr/acpi/acpi.h>

		BUILD_ASSERT(CONFIG_MP_MAX_NUM_CPUS <= 4, "Only supports max 4 CPUs");

		@@ -142,13 +142,12 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
		uint8_t vector = ((unsigned long) x86_ap_start) >> 12;
		uint8_t apic_id;

		if (IS_ENABLED(CONFIG_X86_ACPI)) {
		struct acpi_cpu *cpu;
		if (IS_ENABLED(CONFIG_ACPI)) {
		struct acpi_madt_local_apic *lapic = acpi_local_apic_get(cpu_num);

		cpu = z_acpi_get_cpu(cpu_num);
		if (cpu != NULL) {
		/* We update the apic_id, x86_ap_start will need it. */
		x86_cpu_loapics[cpu_num] = cpu->apic_id;
		if (lapic != NULL) {
		/* We update the apic_id, __start will need it. */
		x86_cpu_loapics[cpu_num] = lapic->Id;
		}
		}

0 → 100644

+53 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2023 Intel Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <zephyr/kernel.h>

		#define DATA_SIZE_K(n) (n * 1024u)
		#define RSDP_SIGNATURE ((uint64_t)0x2052545020445352)
		#define EBDA_ADD (0x040e)
		#define BIOS_RODATA_ADD (0xe0000)
		#define BIOS_EXT_DATA_LOW (0x80000UL)
		#define BIOS_EXT_DATA_HIGH (0x100000UL)

		static uintptr_t bios_search_rsdp_buff(uintptr_t search_phy_add, uint32_t search_length)
		{
		uint64_t *search_buff;

		z_phys_map((uint8_t **)&search_buff, search_phy_add, search_length, 0);
		if (!search_buff) {
		return 0;
		}

		for (int i = 0; i < search_length / 8u; i++) {
		if (search_buff[i] == RSDP_SIGNATURE) {
		z_phys_unmap((uint8_t *)search_buff, search_length);
		return (search_phy_add + (i * 8u));
		}
		}
		z_phys_unmap((uint8_t *)search_buff, search_length);

		return 0;
		}

		void *bios_acpi_rsdp_get(void)
		{
		uint8_t bios_ext_data, zero_page_base;
		uintptr_t search_phy_add, rsdp_phy_add;

		z_phys_map(&zero_page_base, 0, DATA_SIZE_K(4u), 0);
		bios_ext_data = EBDA_ADD + zero_page_base;
		search_phy_add = (uintptr_t)(((uint16_t )bios_ext_data) << 4u);
		z_phys_unmap(zero_page_base, DATA_SIZE_K(4u));

		if ((search_phy_add >= BIOS_EXT_DATA_LOW) && (search_phy_add < BIOS_EXT_DATA_HIGH)) {
		rsdp_phy_add = bios_search_rsdp_buff(search_phy_add, DATA_SIZE_K(1u));
		if (rsdp_phy_add) {
		return (void *)rsdp_phy_add;
		}
		}
		return (void *)bios_search_rsdp_buff(BIOS_RODATA_ADD, DATA_SIZE_K(128u));
		}

+11 −11

Original line number	Diff line number	Diff line
		@@ -8,8 +8,8 @@
		#include <zephyr/sys/device_mmio.h>
		#include <zephyr/drivers/pcie/pcie.h>

		#ifdef CONFIG_X86_ACPI
		#include <zephyr/arch/x86/acpi.h>
		#ifdef CONFIG_ACPI
		#include <zephyr/acpi/acpi.h>
		#endif

		#ifdef CONFIG_PCIE_MSI
		@@ -35,26 +35,26 @@ static bool do_pcie_mmio_cfg;

		static void pcie_mm_init(void)
		{
		#ifdef CONFIG_X86_ACPI
		struct acpi_mcfg *m = z_acpi_find_table(ACPI_MCFG_SIGNATURE);
		#ifdef CONFIG_ACPI
		struct acpi_mcfg *m = acpi_table_get("MCFG", 0);

		if (m != NULL) {
		int n = (m->sdt.length - sizeof(*m)) / sizeof(m->pci_segs[0]);
		int n = (m->header.Length - sizeof(*m)) / sizeof(m->pci_segs[0]);

		for (int i = 0; i < n && i < MAX_PCI_BUS_SEGMENTS; i++) {
		size_t size;
		uintptr_t phys_addr;

		bus_segs[i].start_bus = m->pci_segs[i].start_bus;
		bus_segs[i].n_buses = 1 + m->pci_segs[i].end_bus
		- m->pci_segs[i].start_bus;
		bus_segs[i].start_bus = m->pci_segs[i].StartBusNumber;
		bus_segs[i].n_buses =
		1 + m->pci_segs[i].EndBusNumber - m->pci_segs[i].StartBusNumber;

		phys_addr = m->pci_segs[i].base_addr;
		phys_addr = m->pci_segs[i].Address;
		/* 32 devices & 8 functions per bus, 4k per device */
		size = bus_segs[i].n_buses * (32 * 8 * 4096);

		device_map((mm_reg_t *)&bus_segs[i].mmio, phys_addr,
		size, K_MEM_CACHE_NONE);
		device_map((mm_reg_t *)&bus_segs[i].mmio, phys_addr, size,
		K_MEM_CACHE_NONE);
		}

		do_pcie_mmio_cfg = true;