Commit a52230b8 authored by Robert Hancock's avatar Robert Hancock Committed by Benjamin Cabé
Browse files

drivers: serial: uart_xlnx_ps: run clang-format 

Updated code formatting with clang-format. No functional change
intended.

Signed-off-by: default avatarRobert Hancock <robert.hancock@calian.com>
parent f4fda91e

drivers/serial/uart_xlnx_ps.c

+29 −64
Changes for drivers/serial/uart_xlnx_ps.c: 29 added lines, 64 removed lines.
Original line number Diff line number Diff line
@@ -302,10 +302,8 @@ static int uart_xlnx_ps_init(const struct device *dev) 


	/* Set initial character length / start/stop bit / parity configuration */

	reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET);

	reg_val &= (~(XUARTPS_MR_CHARLEN_MASK | XUARTPS_MR_STOPMODE_MASK |

		    XUARTPS_MR_PARITY_MASK));

	reg_val |= XUARTPS_MR_CHARLEN_8_BIT | XUARTPS_MR_STOPMODE_1_BIT |

		   XUARTPS_MR_PARITY_NONE;

	reg_val &= (~(XUARTPS_MR_CHARLEN_MASK | XUARTPS_MR_STOPMODE_MASK | XUARTPS_MR_PARITY_MASK));

	reg_val |= XUARTPS_MR_CHARLEN_8_BIT | XUARTPS_MR_STOPMODE_1_BIT | XUARTPS_MR_PARITY_NONE;

	sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET);



	/* Set RX FIFO trigger at 1 data bytes. */
@@ -403,9 +401,7 @@ static void uart_xlnx_ps_poll_out(const struct device *dev, unsigned char c) 
 *         as all parity modes supported by the API are also supported

 *         by the hardware.

 */

static inline bool uart_xlnx_ps_cfg2ll_parity(

	uint32_t *mode_reg,

	enum uart_config_parity parity)

static inline bool uart_xlnx_ps_cfg2ll_parity(uint32_t *mode_reg, enum uart_config_parity parity)

{

	/*

	 * Translate the new parity configuration to the mode register's
@@ -457,8 +453,7 @@ static inline bool uart_xlnx_ps_cfg2ll_parity( 
 * @return Indication of success or failure in case of an unsupported

 *         stop bit configuration being provided by the caller.

 */

static inline bool uart_xlnx_ps_cfg2ll_stopbits(

	uint32_t *mode_reg,

static inline bool uart_xlnx_ps_cfg2ll_stopbits(uint32_t *mode_reg,

						enum uart_config_stop_bits stopbits)

{

	/*
@@ -507,8 +502,7 @@ static inline bool uart_xlnx_ps_cfg2ll_stopbits( 
 * @return Indication of success or failure in case of an unsupported

 *         data bit configuration being provided by the caller.

 */

static inline bool uart_xlnx_ps_cfg2ll_databits(

	uint32_t *mode_reg,

static inline bool uart_xlnx_ps_cfg2ll_databits(uint32_t *mode_reg,

						enum uart_config_data_bits databits)

{

	/*
@@ -559,8 +553,7 @@ static inline bool uart_xlnx_ps_cfg2ll_databits( 
 * @return Indication of success or failure in case of an unsupported

 *         flow control configuration being provided by the caller.

 */

static inline bool uart_xlnx_ps_cfg2ll_hwctrl(

	uint32_t *modemcr_reg,

static inline bool uart_xlnx_ps_cfg2ll_hwctrl(uint32_t *modemcr_reg,

					      enum uart_config_flow_control hwctrl)

{

	/*
@@ -595,11 +588,9 @@ static inline bool uart_xlnx_ps_cfg2ll_hwctrl( 
 * @return 0 if the configuration completed successfully, ENOTSUP

 *         error if an unsupported configuration parameter is detected.

 */

static int uart_xlnx_ps_configure(const struct device *dev,

				  const struct uart_config *cfg)

static int uart_xlnx_ps_configure(const struct device *dev, const struct uart_config *cfg)

{

	struct uart_xlnx_ps_dev_config *dev_cfg =

	(struct uart_xlnx_ps_dev_config *)dev->config;

	struct uart_xlnx_ps_dev_config *dev_cfg = (struct uart_xlnx_ps_dev_config *)dev->config;



	uintptr_t reg_base = DEVICE_MMIO_GET(dev);

	uint32_t mode_reg = 0;
@@ -655,8 +646,7 @@ static int uart_xlnx_ps_configure(const struct device *dev, 
 * @return The current parity setting mapped to the UART driver API's

 *         enum type.

 */

static inline enum uart_config_parity uart_xlnx_ps_ll2cfg_parity(

	uint32_t mode_reg)

static inline enum uart_config_parity uart_xlnx_ps_ll2cfg_parity(uint32_t mode_reg)

{

	/*

	 * Obtain the current parity configuration from the mode register's
@@ -697,8 +687,7 @@ static inline enum uart_config_parity uart_xlnx_ps_ll2cfg_parity( 
 * @return The current stop bit setting mapped to the UART driver API's

 *         enum type.

 */

static inline enum uart_config_stop_bits uart_xlnx_ps_ll2cfg_stopbits(

	uint32_t mode_reg)

static inline enum uart_config_stop_bits uart_xlnx_ps_ll2cfg_stopbits(uint32_t mode_reg)

{

	/*

	 * Obtain the current stop bit configuration from the mode register's
@@ -734,8 +723,7 @@ static inline enum uart_config_stop_bits uart_xlnx_ps_ll2cfg_stopbits( 
 * @return The current data bit setting mapped to the UART driver API's

 *         enum type.

 */

static inline enum uart_config_data_bits uart_xlnx_ps_ll2cfg_databits(

	uint32_t mode_reg)

static inline enum uart_config_data_bits uart_xlnx_ps_ll2cfg_databits(uint32_t mode_reg)

{

	/*

	 * Obtain the current data bit configuration from the mode register's
@@ -770,8 +758,7 @@ static inline enum uart_config_data_bits uart_xlnx_ps_ll2cfg_databits( 
 * @return The current flow control setting mapped to the UART driver API's

 *         enum type.

 */

static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl(

	uint32_t modemcr_reg)

static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl(uint32_t modemcr_reg)

{

	/*

	 * Obtain the current flow control configuration from the modem
@@ -780,8 +767,7 @@ static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl( 
	 *  1b : RTS/CTS

	 */



	if ((modemcr_reg & XUARTPS_MODEMCR_FCM_MASK)

		== XUARTPS_MODEMCR_FCM_RTS_CTS) {

	if ((modemcr_reg & XUARTPS_MODEMCR_FCM_MASK) == XUARTPS_MODEMCR_FCM_RTS_CTS) {

		return UART_CFG_FLOW_CTRL_RTS_CTS;

	}
@@ -802,8 +788,7 @@ static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl( 
 *

 * @return always 0.

 */

static int uart_xlnx_ps_config_get(const struct device *dev,

				   struct uart_config *cfg)

static int uart_xlnx_ps_config_get(const struct device *dev, struct uart_config *cfg)

{

	const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
@@ -838,9 +823,7 @@ static int uart_xlnx_ps_config_get(const struct device *dev, 
 *

 * @return Number of bytes sent

 */

static int uart_xlnx_ps_fifo_fill(const struct device *dev,

				  const uint8_t *tx_data,

				  int size)

static int uart_xlnx_ps_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)

{

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);

	uint32_t data_iter = 0;
@@ -865,16 +848,14 @@ static int uart_xlnx_ps_fifo_fill(const struct device *dev, 
 *

 * @return Number of bytes read

 */

static int uart_xlnx_ps_fifo_read(const struct device *dev, uint8_t *rx_data,

				  const int size)

static int uart_xlnx_ps_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)

{

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);

	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);

	int inum = 0;



	while (inum < size && (reg_val & XUARTPS_SR_RXEMPTY) == 0) {

		rx_data[inum] = (uint8_t)sys_read32(reg_base

				+ XUARTPS_FIFO_OFFSET);

		rx_data[inum] = (uint8_t)sys_read32(reg_base + XUARTPS_FIFO_OFFSET);

		inum++;

		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);

	}
@@ -891,9 +872,7 @@ static void uart_xlnx_ps_irq_tx_enable(const struct device *dev) 
{

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);



	sys_write32(

		(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY),

		reg_base + XUARTPS_IER_OFFSET);

	sys_write32((XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY), reg_base + XUARTPS_IER_OFFSET);

}



/**
@@ -905,9 +884,7 @@ static void uart_xlnx_ps_irq_tx_disable(const struct device *dev) 
{

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);



	sys_write32(

		(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY),

		reg_base + XUARTPS_IDR_OFFSET);

	sys_write32((XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY), reg_base + XUARTPS_IDR_OFFSET);

}



/**
@@ -1001,8 +978,7 @@ static void uart_xlnx_ps_irq_err_enable(const struct device *dev) 
{

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);



	sys_write32(

		  XUARTPS_IXR_TOVR    /* [12] Transmitter FIFO Overflow */

	sys_write32(XUARTPS_IXR_TOVR              /* [12] Transmitter FIFO Overflow */

			    | XUARTPS_IXR_TOUT    /* [8]  Receiver Timerout */

			    | XUARTPS_IXR_PARITY  /* [7]  Parity Error */

			    | XUARTPS_IXR_FRAMING /* [6]  Receiver Framing Error */
@@ -1021,8 +997,7 @@ static void uart_xlnx_ps_irq_err_disable(const struct device *dev) 
{

	uintptr_t reg_base = DEVICE_MMIO_GET(dev);



	sys_write32(

		  XUARTPS_IXR_TOVR    /* [12] Transmitter FIFO Overflow */

	sys_write32(XUARTPS_IXR_TOVR              /* [12] Transmitter FIFO Overflow */

			    | XUARTPS_IXR_TOUT    /* [8]  Receiver Timerout */

			    | XUARTPS_IXR_PARITY  /* [7]  Parity Error */

			    | XUARTPS_IXR_FRAMING /* [6]  Receiver Framing Error */
@@ -1070,8 +1045,7 @@ static int uart_xlnx_ps_irq_update(const struct device *dev) 
 * @param cb Callback function pointer.

 */

static void uart_xlnx_ps_irq_callback_set(const struct device *dev,

					    uart_irq_callback_user_data_t cb,

					    void *cb_data)

					  uart_irq_callback_user_data_t cb, void *cb_data)

{

	struct uart_xlnx_ps_dev_data_t *dev_data = dev->data;
@@ -1123,16 +1097,13 @@ static DEVICE_API(uart, uart_xlnx_ps_driver_api) = { 


#ifdef CONFIG_UART_INTERRUPT_DRIVEN



#define UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) \

	.irq_config_func = uart_xlnx_ps_irq_config_##port,

#define UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) .irq_config_func = uart_xlnx_ps_irq_config_##port,



#define UART_XLNX_PS_IRQ_CONF_FUNC(port)                                                           \

	static void uart_xlnx_ps_irq_config_##port(const struct device *dev)                       \

	{                                                                                          \

	IRQ_CONNECT(DT_INST_IRQN(port), \

	DT_INST_IRQ(port, priority), \

	uart_xlnx_ps_isr, DEVICE_DT_INST_GET(port), \

	0); \

		IRQ_CONNECT(DT_INST_IRQN(port), DT_INST_IRQ(port, priority), uart_xlnx_ps_isr,     \

			    DEVICE_DT_INST_GET(port), 0);                                          \

		irq_enable(DT_INST_IRQN(port));                                                    \

	}
@@ -1159,18 +1130,12 @@ static struct uart_xlnx_ps_dev_config uart_xlnx_ps_dev_cfg_##port = { \ 
		DEVICE_MMIO_ROM_INIT(DT_DRV_INST(port)),                                           \

		.sys_clk_freq = DT_INST_PROP(port, clock_frequency),                               \

		.baud_rate = DT_INST_PROP(port, current_speed),                                    \

	UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) \

	UART_XLNX_PS_PINCTRL_INIT(port) \

}

		UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) UART_XLNX_PS_PINCTRL_INIT(port)}



#define UART_XLNX_PS_INIT(port)                                                                    \

DEVICE_DT_INST_DEFINE(port, \

	uart_xlnx_ps_init, \

	NULL, \

	&uart_xlnx_ps_dev_data_##port, \

	&uart_xlnx_ps_dev_cfg_##port, \

	PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \

	&uart_xlnx_ps_driver_api)

	DEVICE_DT_INST_DEFINE(port, uart_xlnx_ps_init, NULL, &uart_xlnx_ps_dev_data_##port,        \

			      &uart_xlnx_ps_dev_cfg_##port, PRE_KERNEL_1,                          \

			      CONFIG_SERIAL_INIT_PRIORITY, &uart_xlnx_ps_driver_api)



#define UART_XLNX_INSTANTIATE(inst)                                                                \

	UART_XLNX_PS_PINCTRL_DEFINE(inst)                                                          \

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