Commit a4740662 authored by Daniel DeGrasse's avatar Daniel DeGrasse Committed by Christopher Friedt
Browse files

boards: mimxrt1024_evk: Add SPI support 



Add support for LPSPI to mimxrt1024_evk. LPSPI1 is exposed on pins
6,8,10, and 12 of J19 of the evaluation board

Signed-off-by: default avatarDaniel DeGrasse <daniel.degrasse@nxp.com>
parent da57f024

boards/arm/mimxrt1024_evk/doc/index.rst

+6 −4
Original line number Diff line number Diff line
@@ -85,6 +85,8 @@ features: 
| UART      | on-chip    | serial port-polling;                |

|           |            | serial port-interrupt               |

+-----------+------------+-------------------------------------+

| SPI       | on-chip    | spi                                 |

+-----------+------------+-------------------------------------+

| ENET      | on-chip    | ethernet                            |

+-----------+------------+-------------------------------------+

| CAN       | on-chip    | can                                 |
@@ -123,13 +125,13 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers. 
+---------------+-----------------+---------------------------+

| GPIO_AD_B0_09 | ENET_RX_DATA01  | Ethernet                  |

+---------------+-----------------+---------------------------+

| GPIO_AD_B0_10 | ENET_RX_DATA00  | Ethernet                  |

| GPIO_AD_B0_10 | ENET_RX_DATA00/LPSPI1_SCK | Ethernet/SPI    |

+---------------+-----------------+---------------------------+

| GPIO_AD_B0_11 | ENET_RX_EN      | Ethernet                  |

| GPIO_AD_B0_11 | ENET_RX_EN/LPSPI1_PCS0 | Ethernet/SPI       |

+---------------+-----------------+---------------------------+

| GPIO_AD_B0_12 | ENET_RX_ER      | Ethernet                  |

| GPIO_AD_B0_12 | ENET_RX_ER/LPSPI1_SDO | Ethernet/SPI        |

+---------------+-----------------+---------------------------+

| GPIO_AD_B0_13 | ENET_TX_EN      | Ethernet                  |

| GPIO_AD_B0_13 | ENET_TX_EN/LPSPI1_SDI | Ethernet/SPI        |

+---------------+-----------------+---------------------------+

| GPIO_AD_B0_14 | ENET_TX_DATA00  | Ethernet                  |

+---------------+-----------------+---------------------------+

boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts

+4 −0
Original line number Diff line number Diff line
@@ -116,3 +116,7 @@ 
&edma0 {

	status = "okay";

};



&lpspi1 {

	status = "okay";

};

boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml

+1 −0
Original line number Diff line number Diff line
@@ -20,3 +20,4 @@ supported: 
  - hwinfo

  - netif:eth

  - watchdog

  - spi

boards/arm/mimxrt1024_evk/pinmux.c

+34 −0
Original line number Diff line number Diff line
@@ -115,6 +115,40 @@ static int mimxrt1024_evk_init(const struct device *dev) 
			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));

#endif



#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI

#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET

	#error "LPSPI1 and ENET share pins on this board, please disable one" \

			"using KConfig or the devicetree"

#else

	/* LPSPI1 CS, SDO, SDI, CLK exposed as pins 6, 8, 10, and 12 on J19 */

	/* GPIO_AD_B0_10 is configured as LPSPI1_SCK */

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK, 0U);

	/* GPIO_AD_B0_11 is configured as LPSPI1_PCS0 */

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0, 0U);

	/* GPIO_AD_B0_12 is configured as LPSPI1_SDO */

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO, 0U);

	/* GPIO_AD_B0_13 is configured as LPSPI1_SDI */

	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI, 0U);



	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK,

			IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |

			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));

	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0,

			IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |

			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));

	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO,

			IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |

			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));

	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI,

			IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |

			IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |

			IOMUXC_SW_PAD_CTL_PAD_DSE(6));

#endif

#endif



	return 0;

}

tests/drivers/spi/spi_loopback/boards/mimxrt1024_evk.conf

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+7 −0
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#

# Copyright (c) 2021, NXP

#

# SPDX-License-Identifier: Apache-2.0

#



CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_1"

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