drivers: gpio: stm32: STM32F7 GPIO support (a229500d) · Commits · Wenxi XU / zephyr

arch/arm/soc/st_stm32/stm32f7/CMakeLists.txt

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		@@ -2,3 +2,4 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
		zephyr_sources(
		soc.c
		)
		zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

+16 −0

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		@@ -12,4 +12,20 @@ gsource "arch/arm/soc/st_stm32/stm32f7/Kconfig.defconfig.stm32f7*"
		config SOC_SERIES
		default "stm32f7"

		if GPIO_STM32

		config GPIO_STM32_PORTD
		default y

		config GPIO_STM32_PORTE
		default y

		config GPIO_STM32_PORTH
		default y

		config GPIO_STM32_PORTI
		default y

		endif # GPIO_STM32

		endif # SOC_SERIES_STM32F7X

+10 −0

0 → 100644

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		/*
		* Copyright (c) 2018 Yurii Hamann
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#ifndef _STM32F7X_GPIO_REGISTERS_H_
		#define _STM32F7X_GPIO_REGISTERS_H_

		/**
		* @brief Driver for GPIO of STM32F7X family processor.
		*
		* Based on reference manual:
		* RM0385 Reference manual STM32F75xxx and STM32F74xxx
		* advanced ARM(r)-based 32-bit MCUs
		*
		* Chapter 6: General-purpose I/Os (GPIOs)
		*/

		/* 6.4 GPIO registers - each GPIO port controls 16 pins */
		struct stm32f7x_gpio {
		u32_t moder;
		u32_t otyper;
		u32_t ospeedr;
		u32_t pupdr;
		u32_t idr;
		u32_t odr;
		u32_t bsrr;
		u32_t lckr;
		u32_t afr[2];
		u32_t brr;
		};

		union syscfg_exticr {
		u32_t val;
		struct {
		u16_t rsvd__16_31;
		u16_t exti;
		} bit;
		};

		/* 7.2 SYSCFG registers */
		struct stm32f7x_syscfg {
		u32_t memrmp;
		u32_t pmc;
		union syscfg_exticr exticr1;
		union syscfg_exticr exticr2;
		union syscfg_exticr exticr3;
		union syscfg_exticr exticr4;
		u32_t cmpcr;
		};

		#endif /* _STM32F7X_GPIO_REGISTERS_H_ */

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		@@ -17,6 +17,10 @@
		#ifndef _STM32F7_SOC_H_
		#define _STM32F7_SOC_H_

		#define GPIO_REG_SIZE 0x400
		/* base address for where GPIO registers start */
		#define GPIO_PORTS_BASE (GPIOA_BASE)

		#ifndef _ASMLANGUAGE

		#include <device.h>