Commit a1048d4f authored by Pieter De Gendt's avatar Pieter De Gendt
Browse files

arch: common: nocache.ld: One nocache MPU region 



Combine the load and noload cache regions for a single MPU aligned block.
This is required to have an MPU region with a size that is a power of 2.

Signed-off-by: default avatarPieter De Gendt <pieter.degendt@basalte.be>
(cherry picked from commit 8f790869)
parent c8cac78c

arch/common/nocache.ld

+2 −12
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) 
#if defined(CONFIG_MMU)

	MMU_ALIGN;

#else

	MPU_ALIGN(_nocache_noload_ram_size);

	MPU_ALIGN(_nocache_ram_size);

#endif

	_nocache_ram_start = .;

	_nocache_noload_ram_start = .;
@@ -23,11 +23,6 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) 


#include <snippets-nocache-section.ld>



#if defined(CONFIG_MMU)

	MMU_ALIGN;

#else

	MPU_ALIGN(_nocache_noload_ram_size);

#endif

	_nocache_noload_ram_end = .;

} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

_nocache_noload_ram_size = _nocache_noload_ram_end - _nocache_noload_ram_start;
@@ -35,11 +30,6 @@ _nocache_noload_ram_size = _nocache_noload_ram_end - _nocache_noload_ram_start; 
/* Non-cached loadable region of RAM and ROM */

SECTION_DATA_PROLOGUE(_NOCACHE_LOAD_SECTION_NAME,,)

{

#if defined(CONFIG_MMU)

	MMU_ALIGN;

#else

	MPU_ALIGN(_nocache_load_ram_size);

#endif

	_nocache_load_ram_start = .;

	*(.nocache_load)

	*(".nocache_load.*")
@@ -47,7 +37,7 @@ SECTION_DATA_PROLOGUE(_NOCACHE_LOAD_SECTION_NAME,,) 
#if defined(CONFIG_MMU)

	MMU_ALIGN;

#else

	MPU_ALIGN(_nocache_load_ram_size);

	MPU_ALIGN(_nocache_ram_size);

#endif

	_nocache_load_ram_end = .;

	_nocache_ram_end = .;

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