Commit 9f19763b authored by Kyle Micallef Bonnici's avatar Kyle Micallef Bonnici Committed by Anas Nashif
Browse files

devicetree: format SoC-level files in dts/riscv 

Applying dts-linter results for SoC-level files in

dts/riscv

Signed-off-by: default avatarKyle Micallef Bonnici <kylebonnici@hotmail.com>
parent 905b9f99

dts/riscv/neorv32.dtsi

+2 −4
Changes for dts/riscv/neorv32.dtsi: 2 added lines, 4 removed lines.
Original line number Diff line number Diff line
@@ -33,8 +33,7 @@ 
				firq: firq {

					#address-cells = <1>;

					interrupt-map-mask = <0x0 0xffffffff>;

					interrupt-map = <

						0  0 &intc 0 16

					interrupt-map = <0 0 &intc 0 16

							 0 1 &intc 0 17

							 0 2 &intc 0 18

							 0 3 &intc 0 19
@@ -49,8 +48,7 @@ 
							 0 12 &intc 0 28

							 0 13 &intc 0 29

							 0 14 &intc 0 30

						0 15 &intc 0 31

					>;

							 0 15 &intc 0 31>;

					#interrupt-cells = <1>;

				};

			};

dts/riscv/renode_riscv32_virt.dtsi

+2 −0
Changes for dts/riscv/renode_riscv32_virt.dtsi: 2 added lines, 0 removed lines.
Original line number Diff line number Diff line
@@ -13,12 +13,14 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			clock-frequency = <0>;

			compatible = "renode,virt", "riscv";

			device_type = "cpu";

			reg = <0>;

			riscv,isa = "rv32imac_zicsr_zifencei";



			hlic: interrupt-controller {

				compatible = "riscv,cpu-intc";

				#address-cells = <0>;

dts/riscv/riscv32-litex-vexriscv.dtsi

+32 −9
Changes for dts/riscv/riscv32-litex-vexriscv.dtsi: 32 added lines, 9 removed lines.
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ 
	compatible = "litex,vexriscv", "litex-dev";

	model = "litex,vexriscv";





	chosen {

		zephyr,entropy = &prbs0;

	};
@@ -20,6 +19,7 @@ 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			clock-frequency = <100000000>;

			compatible = "litex,vexriscv-standard", "riscv";
@@ -29,11 +29,13 @@ 
			status = "okay";

		};

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "litex,vexriscv";

		ranges;



		ctrl0: soc_controller@e0000000 {

			compatible = "litex,soc-controller";

			reg = <0xe0000000 0x4
@@ -43,6 +45,7 @@ 
				    "scratch",

				    "bus_errors";

		};



		intc0: interrupt-controller@bc0 {

			compatible = "litex,vexriscv-intc0";

			#address-cells = <0>;
@@ -52,6 +55,7 @@ 
			reg-names = "irq_mask", "irq_pending";

			riscv,max-priority = <7>;

		};



		uart0: serial@e0001800 {

			compatible = "litex,uart";

			interrupt-parent = <&intc0>;
@@ -64,8 +68,7 @@ 
			       0xe0001814 0x4

			       0xe0001818 0x4

			       0xe000181c 0x4>;

			reg-names =

				"rxtx",

			reg-names = "rxtx",

				    "txfull",

				    "rxempty",

				    "ev_status",
@@ -75,6 +78,7 @@ 
				    "rxfull";

			status = "disabled";

		};



		spi0: spi@e0002000 {

			compatible = "litex,spi";

			reg = <0xe0002000 0x4
@@ -93,6 +97,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi1: spi@e000c000 {

			compatible = "litex,spi-litespi";

			interrupt-parent = <&intc0>;
@@ -119,12 +124,14 @@ 
			interrupts = <9 0>;

			#address-cells = <1>;

			#size-cells = <0>;



			spiflash0: flash@0 {

				compatible = "jedec,spi-nor";

				reg = <0>;

				spi-max-frequency = <10000000>;

			};

		};



		timer0: timer@e0002800 {

			compatible = "litex,timer0";

			interrupt-parent = <&intc0>;
@@ -139,8 +146,7 @@ 
			       0xe000281c 0x4

			       0xe0002820 0x4

			       0xe0002824 0x8>;

			reg-names =

				"load",

			reg-names = "load",

				    "reload",

				    "en",

				    "update_value",
@@ -152,6 +158,7 @@ 
				    "uptime_cycles";

			status = "disabled";

		};



		wdt0: watchdog@e000d000 {

			compatible = "litex,watchdog";

			interrupt-parent = <&intc0>;
@@ -169,6 +176,7 @@ 
				    "ev_enable";

			interrupts = <8 15>;

		};



		mdio0: mdio@e0008000 {

			compatible = "litex,liteeth-mdio";

			reg = <0xe0008000 0x4>,
@@ -186,6 +194,7 @@ 
				reg = <1>;

			};

		};



		eth0: ethernet@e0009800 {

			compatible = "litex,liteeth";

			interrupt-parent = <&intc0>;
@@ -224,17 +233,20 @@ 
			phy-handle = <&phy0>;

			status = "disabled";

		};



		dna0: dna@e0003800 {

			compatible = "litex,dna0";

			/* DNA data is 57-bits long,

			so it requires 8 bytes.

			In LiteX each 32-bit register holds

			only a single byte of meaningful data,

			hence 8 registers. */

			 * so it requires 8 bytes.

			 * In LiteX each 32-bit register holds

			 * only a single byte of meaningful data,

			 * hence 8 registers.

			 */

			reg = <0xe0003800 0x20>;

			reg-names = "mem";

			status = "disabled";

		};



		i2c0: i2c@e0005000 {

			compatible = "litex,i2c";

			reg = <0xe0005000 0x4 0xe0005004 0x4>;
@@ -244,6 +256,7 @@ 
			#size-cells = <0>;

			status = "disabled";

		};



		i2c1: i2c@e000d800 {

			compatible = "litex,litei2c";

			interrupt-parent = <&intc0>;
@@ -271,6 +284,7 @@ 
			#size-cells = <0>;

			status = "disabled";

		};



		gpio_out: gpio@e0005800 {

			compatible = "litex,gpio";

			reg = <0xe0005800 0x4>;
@@ -281,6 +295,7 @@ 
			gpio-controller;

			#gpio-cells = <2>;

		};



		gpio_in: gpio@e0006000 {

			compatible = "litex,gpio";

			reg = <0xe0006000 0x4
@@ -300,12 +315,14 @@ 
			gpio-controller;

			#gpio-cells = <2>;

		};



		prbs0: prbs@e0006800 {

			compatible = "litex,prbs";

			reg = <0xe0006800 0x4>;

			reg-names = "status";

			status = "disabled";

		};



		pwm0: pwm@e0007000 {

			compatible = "litex,pwm";

			reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
@@ -313,6 +330,7 @@ 
			status = "disabled";

			#pwm-cells = <2>;

		};



		i2s_rx: i2s_rx@e000a800 {

			compatible = "litex,i2s";

			reg = <0xe000a800 0x4
@@ -336,6 +354,7 @@ 
			fifo-depth = <256>;

			status = "disabled";

		};



		i2s_tx: i2s_tx@e000b000 {

			compatible = "litex,i2s";

			reg = <0xe000b000 0x4
@@ -359,9 +378,11 @@ 
			fifo-depth = <256>;

			status = "disabled";

		};



		clock-outputs {

			#address-cells = <1>;

			#size-cells = <0>;



			clk0: clock-controller@0 {

				#clock-cells = <1>;

				reg = <0>;
@@ -375,6 +396,7 @@ 
				litex,clock-margin-exp = <2>;

				status = "disabled";

			};



			clk1: clock-controller@1 {

				#clock-cells = <1>;

				reg = <1>;
@@ -389,6 +411,7 @@ 
				status = "disabled";

			};

		};



		clock0: clock@e0004800 {

			compatible = "litex,clk";

			reg = <0xe0004800 0x4

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