Commit 9dd25adc authored by Nathan Olff's avatar Nathan Olff Committed by Carles Cufi
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dts: add fracn to STM32H7 PLL clocks 



add fracn to STM32H7 pll clock binding

Signed-off-by: default avatarNathan Olff <nathan@kickmaker.net>
parent 4b68043e

dts/bindings/clock/st,stm32h7-pll-clock.yaml

+6 −0
Original line number Diff line number Diff line
@@ -65,3 +65,9 @@ properties: 
    description: |

        PLL division factor for pllx_r_ck

        Valid range: 1 - 128



  fracn:

    type: int

    description: |

        PLLx FRACN value

        Valid range: 0 - 8191

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