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Commit 9d51d914 authored by Henrik Brix Andersen's avatar Henrik Brix Andersen Committed by Carles Cufí
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soc: arm: xilinx: zynq7000: default to 1 CPU core 



Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.

Signed-off-by: default avatarHenrik Brix Andersen <henrik@brixandersen.dk>
parent a833d879
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