Commit 9bf75d1e authored by Huifeng Zhang's avatar Huifeng Zhang Committed by Carles Cufi
Browse files

board: fvp_base_revc_2xaemv8a: change the uart interrupts values 



There are some wrong interrupt-cells values of the uart nodes in this
board. The order of the arm,gic interrupt-cells should be type, irq,
flags and priority.

Signed-off-by: default avatarHuifeng Zhang <Huifeng.Zhang@arm.com>
parent 3d58697d

boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts

+4 −4
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ 
			compatible = "arm,pl011";

			reg = <0x1c090000 0x1000>;

			status = "disabled";

			interrupts = <GIC_SPI 5 0 IRQ_TYPE_LEVEL>;

			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_5";

			clocks = <&uartclk>;

		};
@@ -109,7 +109,7 @@ 
			compatible = "arm,pl011";

			reg = <0x1c0a0000 0x1000>;

			status = "disabled";

			interrupts = <GIC_SPI 6 0 IRQ_TYPE_LEVEL>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_6";

			clocks = <&uartclk>;

		};
@@ -118,7 +118,7 @@ 
			compatible = "arm,pl011";

			reg = <0x1c0b0000 0x1000>;

			status = "disabled";

			interrupts = <GIC_SPI 7 0 IRQ_TYPE_LEVEL>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_7";

			clocks = <&uartclk>;

		};
@@ -127,7 +127,7 @@ 
			compatible = "arm,pl011";

			reg = <0x1c0c0000 0x1000>;

			status = "disabled";

			interrupts = <GIC_SPI 8 0 IRQ_TYPE_LEVEL>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

			interrupt-names = "irq_8";

			clocks = <&uartclk>;

		};

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