drivers: pinctrl: nrf: add flag to signal the FAST_ACTIVE1 peripherals (9925ec99) · Commits · Wenxi XU / zephyr

drivers/pinctrl/pinctrl_nrf.c

+32 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,9 @@
		#include <zephyr/drivers/pinctrl.h>

		#include <hal/nrf_gpio.h>
		#ifdef CONFIG_SOC_NRF54H20_GPD
		#include <nrf/gpd.h>
		#endif

		BUILD_ASSERT(((NRF_PULL_NONE == NRF_GPIO_PIN_NOPULL) &&
		(NRF_PULL_DOWN == NRF_GPIO_PIN_PULLDOWN) &&
		@@ -352,6 +355,21 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
		if (psel != PSEL_DISCONNECTED) {
		uint32_t pin = psel;

		#ifdef CONFIG_SOC_NRF54H20_GPD
		if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) {
		int ret;
		uint32_t d_pin = pin;
		NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&d_pin);

		ret = nrf_gpd_request(NRF_GPD_SLOW_ACTIVE);
		if (ret < 0) {
		return ret;
		}

		port->RETAINCLR = BIT(d_pin);
		}
		#endif /* CONFIG_SOC_NRF54H20_GPD */

		if (write != NO_WRITE) {
		nrf_gpio_pin_write(pin, write);
		}
		@@ -367,6 +385,20 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
		#if NRF_GPIO_HAS_CLOCKPIN
		nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i]));
		#endif
		#ifdef CONFIG_SOC_NRF54H20_GPD
		if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) {
		int ret;
		uint32_t d_pin = pin;
		NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&d_pin);

		port->RETAINSET = BIT(d_pin);

		ret = nrf_gpd_release(NRF_GPD_SLOW_ACTIVE);
		if (ret < 0) {
		return ret;
		}
		}
		#endif /* CONFIG_SOC_NRF54H20_GPD */
		}
		}

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

+9 −3

Original line number	Diff line number	Diff line
		@@ -10,7 +10,9 @@
		* The whole nRF pin configuration information is encoded in a 32-bit bitfield
		* organized as follows:
		*
		* - 31..18: Pin function.
		* - 31..24: Pin function.
		* - 19-23: Reserved.
		* - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
		* - 17: Clockpin enable.
		* - 16: Pin inversion mode.
		* - 15: Pin low power mode.
		@@ -25,9 +27,13 @@
		*/

		/** Position of the function field. */
		#define NRF_FUN_POS 18U
		#define NRF_FUN_POS 24U
		/** Mask for the function field. */
		#define NRF_FUN_MSK 0x3FFFU
		#define NRF_FUN_MSK 0xFFU
		/** Position of the GPD FAST ACTIVE1 */
		#define NRF_GPD_FAST_ACTIVE1_POS 18U
		/** Mask for the GPD FAST ACTIVE1 */
		#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U
		/** Position of the clockpin enable field. */
		#define NRF_CLOCKPIN_ENABLE_POS 17U
		/** Mask for the clockpin enable field. */

soc/nordic/common/pinctrl_soc.h

+21 −1

Original line number	Diff line number	Diff line
		@@ -14,6 +14,7 @@

		#include <zephyr/devicetree.h>
		#include <zephyr/dt-bindings/pinctrl/nrf-pinctrl.h>
		#include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
		#include <zephyr/types.h>

		#ifdef __cplusplus
		@@ -55,6 +56,16 @@ typedef uint32_t pinctrl_soc_pin_t;
		(), NRF_GET_FUN(DT_PROP_BY_IDX(node_id, prop, idx))) \
		0)), (0))

		/**
		* @brief Utility macro to get the GPD_FAST_ACTIVE1 flag
		*
		* @param p_node_id Parent node identifier.
		*/
		#define Z_GET_GPD_FAST_ACTIVE1(p_node_id) \
		COND_CODE_1(DT_NODE_HAS_PROP(p_node_id, power_domains), \
		((DT_PHA(p_node_id, power_domains, id) == \
		NRF_GPD_FAST_ACTIVE1) << NRF_GPD_FAST_ACTIVE1_POS), (0))

		/**
		* @brief Utility macro to initialize each pin.
		*
		@@ -70,7 +81,8 @@ typedef uint32_t pinctrl_soc_pin_t;
		(DT_PROP(node_id, nordic_drive_mode) << NRF_DRIVE_POS) \| \
		((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) \|\
		(DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) \| \
		Z_GET_CLOCKPIN_ENABLE(node_id, prop, idx, p_node_id) \
		Z_GET_CLOCKPIN_ENABLE(node_id, prop, idx, p_node_id) \| \
		Z_GET_GPD_FAST_ACTIVE1(p_node_id) \
		),

		/**
		@@ -99,6 +111,14 @@ typedef uint32_t pinctrl_soc_pin_t;
		#define NRF_GET_CLOCKPIN_ENABLE(pincfg) \
		(((pincfg) >> NRF_CLOCKPIN_ENABLE_POS) & NRF_CLOCKPIN_ENABLE_MSK)

		/**
		* @brief Utility macro to obtain GPD_FAST_ACTIVE1 flag
		*
		* @param pincfg Pin configuration bit field.
		*/
		#define NRF_GET_GPD_FAST_ACTIVE1(pincfg) \
		(((pincfg) >> NRF_GPD_FAST_ACTIVE1_POS) & NRF_GPD_FAST_ACTIVE1_MSK)

		/**
		* @brief Utility macro to obtain pin inversion flag.
		*

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