Commit 963a707a authored by Glauber Maroto Ferreira's avatar Glauber Maroto Ferreira Committed by Anas Nashif
Browse files

soc: esp32s2: refactor cache and bss initialization 



- refactors cache initialization functions by moving it from
soc.c and placing it in soc_cache.c
- moves SPIRAM's bss zeroing before SPIRAM initialization

Signed-off-by: default avatarGlauber Maroto Ferreira <glauber.ferreira@espressif.com>
parent c5857dc0

soc/xtensa/esp32s2/CMakeLists.txt

+1 −0
Original line number Diff line number Diff line
@@ -2,4 +2,5 @@ 


zephyr_sources(

  soc.c

  soc_cache.c

  )

soc/xtensa/esp32s2/soc.c

+8 −60
Original line number Diff line number Diff line
@@ -59,32 +59,7 @@ void __attribute__((section(".iram1"))) __start(void) 
	 * Configure the mode of instruction cache :

	 * cache size, cache associated ways, cache line size.

	 */

	cache_size_t cache_size;

	cache_ways_t cache_ways;

	cache_line_size_t cache_line_size;



#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,

			CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);

	cache_size = CACHE_SIZE_8KB;

#else

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,

			CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);

	cache_size = CACHE_SIZE_16KB;

#endif



	cache_ways = CACHE_4WAYS_ASSOC;



#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B

	cache_line_size = CACHE_LINE_SIZE_16B;

#else

	cache_line_size = CACHE_LINE_SIZE_32B;

#endif



	esp_rom_Cache_Suspend_ICache();

	esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);

	esp_rom_Cache_Invalidate_ICache_All();

	esp_rom_Cache_Resume_ICache(0);

	esp_config_instruction_cache_mode();



	/*

	 * If we need use SPIRAM, we should use data cache, or if we want to
@@ -93,36 +68,7 @@ void __attribute__((section(".iram1"))) __start(void) 
	 * line size.

	 * Enable data cache, so if we don't use SPIRAM, it just works.

	 */

#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB

#if CONFIG_ESP32S2_DATA_CACHE_8KB

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,

			CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);

	cache_size = CACHE_SIZE_8KB;

#else

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,

			CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);

	cache_size = CACHE_SIZE_16KB;

#endif

#else

#if CONFIG_ESP32S2_DATA_CACHE_8KB

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,

			CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);

	cache_size = CACHE_SIZE_8KB;

#else

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,

			CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);

	cache_size = CACHE_SIZE_16KB;

#endif

#endif



	cache_ways = CACHE_4WAYS_ASSOC;

#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B

	cache_line_size = CACHE_LINE_SIZE_16B;

#else

	cache_line_size = CACHE_LINE_SIZE_32B;

#endif

	esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);

	esp_rom_Cache_Invalidate_DCache_All();

	esp_config_data_cache_mode();

	esp_rom_Cache_Enable_DCache(0);



#if !CONFIG_BOOTLOADER_ESP_IDF
@@ -165,6 +111,11 @@ void __attribute__((section(".iram1"))) __start(void) 
#endif



#if CONFIG_ESP_SPIRAM



	memset(&_ext_ram_bss_start,

		0,

		(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));



	esp_err_t err = esp_spiram_init();



	if (err != ESP_OK) {
@@ -177,10 +128,7 @@ void __attribute__((section(".iram1"))) __start(void) 
		abort();

	}



	memset(&_ext_ram_bss_start,

		0,

		(&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start));

#endif

#endif /* CONFIG_ESP_SPIRAM */



/* Scheduler is not started at this point. Hence, guard functions

 * must be initialized after esp_spiram_init_cache which internally

soc/xtensa/esp32s2/soc.h

+4 −0
Original line number Diff line number Diff line
@@ -62,4 +62,8 @@ extern uint8_t g_rom_spiflash_dummy_len_plus[]; 


extern uint32_t esp_rom_g_ticks_per_us_pro;



/* cache initialization functions */

void IRAM_ATTR esp_config_instruction_cache_mode(void);

void IRAM_ATTR esp_config_data_cache_mode(void);



#endif /* __SOC_H__ */

soc/xtensa/esp32s2/soc_cache.c

0 → 100644
+92 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include "soc.h"



/*

 * Instruction Cache definitions

 */

#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)

#define ESP32S2_ICACHE_SIZE CACHE_SIZE_8KB

#else

#define ESP32S2_ICACHE_SIZE CACHE_SIZE_16KB

#endif



#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B)

#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B

#else

#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B

#endif



/*

 * Data Cache definitions

 */

#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)

#define ESP32S2_DCACHE_SIZE CACHE_SIZE_8KB

#else

#define ESP32S2_DCACHE_SIZE CACHE_SIZE_16KB

#endif



#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)

#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B

#else

#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B

#endif



void IRAM_ATTR esp_config_instruction_cache_mode(void)

{

	cache_size_t cache_size;

	cache_ways_t cache_ways;

	cache_line_size_t cache_line_size;



#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,

				CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);

#else

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,

				CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);

#endif



	cache_size = ESP32S2_ICACHE_SIZE;

	cache_ways = CACHE_4WAYS_ASSOC;

	cache_line_size = ESP32S2_ICACHE_LINE_SIZE;



	esp_rom_Cache_Suspend_ICache();

	esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);

	esp_rom_Cache_Invalidate_ICache_All();

	esp_rom_Cache_Resume_ICache(0);

}



void IRAM_ATTR esp_config_data_cache_mode(void)

{

	cache_size_t cache_size;

	cache_ways_t cache_ways;

	cache_line_size_t cache_line_size;



#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB

#if CONFIG_ESP32S2_DATA_CACHE_8KB

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,

				CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);

#else

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,

				CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);

#endif

#else

#if CONFIG_ESP32S2_DATA_CACHE_8KB

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,

				CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);

#else

	esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,

				CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);

#endif

#endif

	cache_size = ESP32S2_DCACHE_SIZE;

	cache_ways = CACHE_4WAYS_ASSOC;

	cache_line_size = ESP32S2_DCACHE_LINE_SIZE;



	esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);

	esp_rom_Cache_Invalidate_DCache_All();

}

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