cache: make arch cache interface parsable by doxygen (94291a0c) · Commits · Wenxi XU / zephyr

include/zephyr/arch/cache.h

+8 −8

Original line number	Diff line number	Diff line
		@@ -25,7 +25,7 @@
		#include <zephyr/arch/xtensa/cache.h>
		#endif

		#if defined(CONFIG_DCACHE)
		#if defined(CONFIG_DCACHE) \|\| defined(__DOXYGEN__)

		/**
		* @brief Enable the d-cache
		@@ -157,7 +157,7 @@ int arch_dcache_flush_and_invd_range(void *addr, size_t size);
		#define cache_data_flush_and_invd_range(addr, size) \
		arch_dcache_flush_and_invd_range(addr, size)

		#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
		#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT) \|\| defined(__DOXYGEN__)

		/**
		*
		@@ -176,11 +176,11 @@ size_t arch_dcache_line_size_get(void);

		#define cache_data_line_size_get arch_dcache_line_size_get

		#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
		#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT \|\| __DOXYGEN__ */

		#endif /* CONFIG_DCACHE */
		#endif /* CONFIG_DCACHE \|\| __DOXYGEN__ */

		#if defined(CONFIG_ICACHE)
		#if defined(CONFIG_ICACHE) \|\| defined(__DOXYGEN__)

		/**
		* @brief Enable the i-cache
		@@ -311,7 +311,7 @@ int arch_icache_flush_and_invd_range(void *addr, size_t size);
		#define cache_instr_flush_and_invd_range(addr, size) \
		arch_icache_flush_and_invd_range(addr, size)

		#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
		#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT) \|\| defined(__DOXYGEN__)

		/**
		*
		@@ -331,9 +331,9 @@ size_t arch_icache_line_size_get(void);

		#define cache_instr_line_size_get arch_icache_line_size_get

		#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
		#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT \|\| __DOXYGEN__ */

		#endif /* CONFIG_ICACHE */
		#endif /* CONFIG_ICACHE \|\| __DOXYGEN__ */

		/**
		* @}