Commit 940c66f8 authored by Najumon B.A's avatar Najumon B.A Committed by Carles Cufi
Browse files

boards: x86: add pci controller node with acpi pnp id 



add acpi pnp/hw id for pcie node to enable support for retreive
interrupt routing information for pci legacy interrupt via acpi

Signed-off-by: default avatarNajumon B.A <najumon.ba@intel.com>
parent 2f3fb49d

boards/x86/intel_adl/Kconfig.defconfig

+0 −2
Original line number Diff line number Diff line
@@ -37,8 +37,6 @@ config HEAP_MEM_POOL_ADD_SIZE_ACPI 
	default 64000000

config MAIN_STACK_SIZE

	default 320000

config ACPI_PRT_BUS_NAME

	default "_SB.PC00"



if SHELL

config SHELL_STACK_SIZE

boards/x86/intel_ehl/Kconfig.defconfig

+0 −4
Original line number Diff line number Diff line
@@ -19,10 +19,6 @@ config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN 
	default n

endif



config ACPI_PRT_BUS_NAME

	depends on ACPI

	default "_SB.PC00"



config HEAP_MEM_POOL_ADD_SIZE_ACPI

	default 2097152

	depends on ACPI

boards/x86/intel_rpl/Kconfig.defconfig

+0 −2
Original line number Diff line number Diff line
@@ -36,8 +36,6 @@ config HEAP_MEM_POOL_ADD_SIZE_ACPI 
	default 64000000

config MAIN_STACK_SIZE

	default 320000

config ACPI_PRT_BUS_NAME

	default "_SB.PC00"



if SHELL

config SHELL_STACK_SIZE

boards/x86/qemu_x86/qemu_x86.dts

+2 −1
Original line number Diff line number Diff line
@@ -49,7 +49,8 @@ 
	pcie0: pcie0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "intel,pcie";

		compatible = "pcie-controller";

		acpi-hid = "PNP0A08";

		ranges;



		can0: can0 {

dts/x86/intel/alder_lake.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -48,7 +48,8 @@ 
	pcie0: pcie0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "intel,pcie";

		compatible = "pcie-controller";

		acpi-hid = "PNP0A08";

		ranges;



		smbus0: smbus0 {

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