Commit 8f5daca5 authored Jul 28, 2025 by CHEN Xing Committed by Chris Friedt Jul 30, 2025

drivers: counter: sam_tc: Big fix for alarm 1



Issue: the alarm 1 do not generate interrupt
There are three compare registers in a SAM TC channel:
RA --> alarm 0
RB --> alarm 1
RC --> top_value
By default the RB/TOIB was configured as an input and no longer
generates interrupt.
Set the direction of TIOB to output for alarm 1 interrupt.

Fixes zephyrproject-rtos/zephyr#85018

Signed-off-by: CHEN Xing <xing.chen@microchip.com>

parent 2f52a1bc

drivers/counter/counter_sam_tc.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -356,6 +356,7 @@ static DEVICE_API(counter, counter_sam_driver_api) = {

		#define COUNTER_SAM_TC_CMR(n) \
		(TC_CMR_TCCLKS(DT_INST_PROP_OR(n, clk, 0)) \
		\| TC_CMR_WAVEFORM_EEVT_XC0 \
		\| TC_CMR_WAVEFORM_WAVSEL_UP_RC \
		\| TC_CMR_WAVE)

Admin message