Commit 8b39d4a6 authored Dec 12, 2024 by Andy Ross Committed by Henrik Brix Andersen Jan 06, 2025

arch/xtensa: Add build-time validation of cache line kconfig



Xtensa cache line sizes aren't an obtuse area of pedantry like they
are in x86.  Different cores already in Zephyr are already using
variant cache line sizes (64 and 128 bytes are both common).

And I tripped over this by using the wrong value because the kconfig
was being inherited (incorrectly) from a default somewhere.

Xtensa exposes the correct value in core-isa.h (well, unless the
toolchain/hal gets messed up).  Add a check to make sure that our
platform kconfig gets it right.

Note that qemu/dc233c was already getting this wrong, leaving the
value at the kconfig default of zero.  That was benign (qemu doesn't
provide any cache emulation for incoherent DMA), but needs to be
fixed.

Signed-off-by: Andy Ross <andyross@google.com>

parent dadd1a34

arch/xtensa/core/prep_c.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,13 @@ extern FUNC_NORETURN void z_cstart(void);
		/* defined by the SoC in case of CONFIG_SOC_HAS_RUNTIME_NUM_CPUS=y */
		extern void soc_num_cpus_init(void);

		/* Make sure the platform configuration matches what the toolchain
		* thinks the hardware is doing.
		*/
		#ifdef CONFIG_DCACHE_LINE_SIZE
		BUILD_ASSERT(CONFIG_DCACHE_LINE_SIZE == XCHAL_DCACHE_LINESIZE);
		#endif

		/**
		*
		* @brief Prepare to and run C code

boards/qemu/xtensa/Kconfig.defconfig

+4 −0

Original line number	Diff line number	Diff line
		@@ -9,4 +9,8 @@ config BUILD_OUTPUT_BIN
		config IPM_CONSOLE_STACK_SIZE
		default 2048 if IPM_CONSOLE_RECEIVER

		# Must match XCHAL_DCACHE_LINESIZE form core-isa.h
		config DCACHE_LINE_SIZE
		default 32

		endif # BOARD_QEMU_XTENSA

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