arch: arm: beetle: Pull in CMSDK header for CMSIS support on Beetle (889b290a) · Commits · Wenxi XU / zephyr

arch/arm/soc/arm/beetle/CMSDK_BEETLE.h

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		/*
		* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		/*
		* This file is derivative of CMSIS V5.00 ARMCM3.h
		*/


		#ifndef CMSDK_BEETLE_H
		#define CMSDK_BEETLE_H

		#ifdef __cplusplus
		extern "C" {
		#endif


		/* ------------------------- Interrupt Number Definition ------------------------ */

		typedef enum IRQn
		{
		/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
		NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
		HardFault_IRQn = -13, /* 3 HardFault Interrupt */
		MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
		BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
		UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
		SVCall_IRQn = -5, /* 11 SV Call Interrupt */
		DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
		PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
		SysTick_IRQn = -1, /* 15 System Tick Interrupt */

		/* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */
		UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
		Spare_IRQn = 1, /* Undefined */
		UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
		I2C0_IRQn = 3, /* I2C 0 Interrupt */
		I2C1_IRQn = 4, /* I2C 1 Interrupt */
		RTC_IRQn = 5, /* RTC Interrupt */
		PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
		PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
		TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
		TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
		DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
		SPI0_IRQn = 11, /* SPI 0 Interrupt */
		UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
		SPI1_IRQn = 13, /* SPI 1 Interrupt */
		QSPI_IRQn = 14, /* QUAD SPI Interrupt */
		DMA_IRQn = 15, /* Reserved for DMA Interrup */
		PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
		PORT0_1_IRQn = 17, /* There are 16 pins in total */
		PORT0_2_IRQn = 18,
		PORT0_3_IRQn = 19,
		PORT0_4_IRQn = 20,
		PORT0_5_IRQn = 21,
		PORT0_6_IRQn = 22,
		PORT0_7_IRQn = 23,
		PORT0_8_IRQn = 24,
		PORT0_9_IRQn = 25,
		PORT0_10_IRQn = 26,
		PORT0_11_IRQn = 27,
		PORT0_12_IRQn = 28,
		PORT0_13_IRQn = 29,
		PORT0_14_IRQn = 30,
		PORT0_15_IRQn = 31,
		SYSERROR_IRQn = 32, /* System Error Interrupt */
		EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
		LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */
		LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */
		LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */
		LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */
		LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */
		LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */
		LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */
		LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */
		PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
		PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
		TRNG_IRQn = 44, /* Random number generator Interrupt */
		} IRQn_Type;


		/* ================================================================================ */
		/* ================ Processor and Core Peripheral Section ================ */
		/* ================================================================================ */

		/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
		#define __CM3_REV 0x0201U /* Core revision r2p1 */
		#define __MPU_PRESENT 1 /* MPU present */
		#define __VTOR_PRESENT 1 /* VTOR present or not */
		#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
		#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */

		#include <core_cm3.h> /* Processor and core peripherals */

		#ifdef __cplusplus
		}
		#endif

		#endif /* CMSDK_BEETLE_H */

arch/arm/soc/arm/beetle/soc.h

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		@@ -12,6 +12,10 @@
		#ifndef _ARM_BEETLE_SOC_H_
		#define _ARM_BEETLE_SOC_H_

		#ifndef _ASMLANGUAGE
		#include "CMSDK_BEETLE.h"
		#endif

		#include "soc_irq.h"

		/*
		@@ -99,7 +103,6 @@
		#include "soc_power.h"
		#include "soc_registers.h"
		#include "soc_pll.h"
		#include "soc_mpu.h"

		/* System Control Register (SYSCON) */
		#define __BEETLE_SYSCON ((volatile struct syscon *)_BEETLE_SYSCON_BASE)

arch/arm/soc/arm/beetle/soc_mpu.h

deleted100644 → 0

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		/*
		* Copyright (c) 2018 Arm Limited.
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		/**
		* @file
		* @brief ARM MPU-related macro definitions.
		*
		* ARM MPU macro definitions required for SOCs
		* which are not ARM CMSIS-compliant.
		*/
		#include <stdint.h>

		#if defined(CONFIG_ARM_MPU)

		#define __IM volatile const
		#define __OM volatile
		#define __IOM volatile

		/**
		\brief Structure type to access the Memory Protection Unit (MPU).
		*/
		typedef struct {
		__IM u32_t TYPE;
		__IOM u32_t CTRL;
		__IOM u32_t RNR;
		__IOM u32_t RBAR;
		__IOM u32_t RASR;
		__IOM u32_t RBAR_A1;
		__IOM u32_t RASR_A1;
		__IOM u32_t RBAR_A2;
		__IOM u32_t RASR_A2;
		__IOM u32_t RBAR_A3;
		__IOM u32_t RASR_A3;
		} MPU_Type;

		#define MPU ((MPU_Type *)0xE000ED90UL)

		/* MPU Control Register Definitions */
		#define MPU_CTRL_PRIVDEFENA_Pos 2U
		#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)

		#define MPU_CTRL_HFNMIENA_Pos 1U
		#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)

		#define MPU_CTRL_ENABLE_Pos 0U
		#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/)

		/* MPU Region Number Register Definitions */
		#define MPU_RNR_REGION_Pos 0U
		#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/)

		/* MPU Region Base Address Register Definitions */
		#define MPU_RBAR_ADDR_Pos 5U
		#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

		#define MPU_RBAR_VALID_Pos 4U
		#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)

		#define MPU_RBAR_REGION_Pos 0U
		#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/)

		/* MPU Region Attribute and Size Register Definitions */
		#define MPU_RASR_ATTRS_Pos 16U
		#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)

		#define MPU_RASR_XN_Pos 28U
		#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)

		#define MPU_RASR_AP_Pos 24U
		#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)

		#define MPU_RASR_TEX_Pos 19U
		#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)

		#define MPU_RASR_S_Pos 18U
		#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)

		#define MPU_RASR_C_Pos 17U
		#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)

		#define MPU_RASR_B_Pos 16U
		#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)

		#define MPU_RASR_SRD_Pos 8U
		#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)

		#define MPU_RASR_SIZE_Pos 1U
		#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)

		#define MPU_RASR_ENABLE_Pos 0U
		#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/)

		#define MPU_TYPE_DREGION_Pos 8U
		#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)

		static inline void ARM_MPU_ClrRegion(u32_t index)
		{
		MPU->RNR = index;
		MPU->RASR = 0U;
		}

		#endif /* CONFIG_ARM_MPU */

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