Commit 8662e0fd authored by Henrik Brix Andersen's avatar Henrik Brix Andersen Committed by Benjamin Cabé
Browse files

soc: neorv32: the NEORV32 does not fully support ISA A extension 

The NEORV32 v1.8.6 does not fully support the RISC-V ISA A
extension. Remove it and enable support for atomic operations in C
regardless of the version used.

Signed-off-by: default avatarHenrik Brix Andersen <henrik@brixandersen.dk>
parent bf369c7d

soc/neorv32/Kconfig

+3 −4
Changes for soc/neorv32/Kconfig: 3 added lines, 4 removed lines.
Original line number Diff line number Diff line 
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>

# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>

# SPDX-License-Identifier: Apache-2.0



config SOC_NEORV32

	select RISCV

	select RISCV_ISA_RV32I

	select RISCV_ISA_EXT_M

	select RISCV_ISA_EXT_A

	select RISCV_ISA_EXT_ZICSR

	select RISCV_ISA_EXT_ZIFENCEI

	select RISCV_PRIVILEGED

	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

	# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO

	select ATOMIC_OPERATIONS_C

	imply XIP



if SOC_NEORV32



config SOC_NEORV32_V1_8_6

	bool "v1.8.6"

	# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO

	select ATOMIC_OPERATIONS_C



config SOC_NEORV32_VERSION

	hex

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