drivers: entropy: stm32: add support for STM32WB09 TRNG (8397d640) · Commits · Wenxi XU / zephyr

drivers/entropy/entropy_stm32.c

+17 −0

Changes for drivers/entropy/entropy_stm32.c: 17 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -77,6 +77,15 @@ BUILD_ASSERT((CONFIG_ENTROPY_STM32_THR_POOL_SIZE &
		(CONFIG_ENTROPY_STM32_THR_POOL_SIZE - 1)) == 0,
		"The CONFIG_ENTROPY_STM32_THR_POOL_SIZE must be a power of 2!");

		/**
		* RM0505 §14.4 "TRNG functional description":
		* To use the TRNG peripheral the system clock frequency must be
		* at least 32 MHz. See also: §6.2.2 "Peripheral clock details".
		*/
		BUILD_ASSERT(!IS_ENABLED(CONFIG_SOC_STM32WB09XX) \|\|
		CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= (32 * 1000 * 1000),
		"STM32WB09: TRNG requires system clock frequency >= 32MHz");

		struct entropy_stm32_rng_dev_cfg {
		struct stm32_pclken *pclken;
		};
		@@ -120,6 +129,14 @@ static int entropy_stm32_suspend(void)
		z_stm32_hsem_lock(CFG_HW_RNG_SEMID, HSEM_LOCK_WAIT_FOREVER);
		#endif /* CONFIG_SOC_SERIES_STM32WBX \|\| CONFIG_STM32H7_DUAL_CORE */
		LL_RNG_Disable(rng);
		#if defined(CONFIG_SOC_STM32WB09XX)
		/* RM0505 Rev.2 §14.4:
		* "After the TRNG IP is disabled by setting CR.DISABLE, in order to
		* properly restart the TRNG IP, the AES_RESET bit must be set to 1
		* (that is, resetting the AES core and restarting all health tests)."
		*/
		LL_RNG_SetAesReset(rng, 1);
		#endif /* CONFIG_SOC_STM32WB09XX */

		#ifdef CONFIG_SOC_SERIES_STM32WBAX
		uint32_t wait_cycles, rng_rate;

drivers/entropy/entropy_stm32.h

+21 −0

Changes for drivers/entropy/entropy_stm32.h: 21 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -29,14 +29,23 @@ static inline void ll_rng_enable_it(RNG_TypeDef *RNGx)
		/* Silence "unused" warning on IRQ-less hardware*/
		ARG_UNUSED(RNGx);
		#if !IRQLESS_TRNG
		# if defined(CONFIG_SOC_STM32WB09XX)
		LL_RNG_EnableEnErrorIrq(RNGx);
		LL_RNG_EnableEnFfFullIrq(RNGx);
		# else
		LL_RNG_EnableIT(RNGx);
		# endif
		#endif /* !IRQLESS_TRNG */
		}

		static inline uint32_t ll_rng_is_active_seis(RNG_TypeDef *RNGx)
		{
		#if defined(CONFIG_SOC_SERIES_STM32WB0X)
		# if defined(CONFIG_SOC_STM32WB09XX)
		return LL_RNG_IsActiveFlag_ENTROPY_ERR(RNGx);
		# else
		return LL_RNG_IsActiveFlag_FAULT(RNGx);
		# endif
		#else
		return LL_RNG_IsActiveFlag_SEIS(RNGx);
		#endif /* CONFIG_SOC_SERIES_STM32WB0X */
		@@ -45,7 +54,11 @@ static inline uint32_t ll_rng_is_active_seis(RNG_TypeDef *RNGx)
		static inline void ll_rng_clear_seis(RNG_TypeDef *RNGx)
		{
		#if defined(CONFIG_SOC_SERIES_STM32WB0X)
		# if defined(CONFIG_SOC_STM32WB09XX)
		LL_RNG_SetResetHealthErrorFlags(RNGx, 1);
		# else
		LL_RNG_ClearFlag_FAULT(RNGx);
		# endif
		#else
		LL_RNG_ClearFlag_SEIS(RNGx);
		#endif /* CONFIG_SOC_SERIES_STM32WB0X */
		@@ -68,7 +81,11 @@ static inline uint32_t ll_rng_is_active_secs(RNG_TypeDef *RNGx)
		static inline uint32_t ll_rng_is_active_drdy(RNG_TypeDef *RNGx)
		{
		#if defined(CONFIG_SOC_SERIES_STM32WB0X)
		# if defined(CONFIG_SOC_STM32WB09XX)
		return LL_RNG_IsActiveFlag_VAL_READY(RNGx);
		# else
		return LL_RNG_IsActiveFlag_RNGRDY(RNGx);
		# endif
		#else
		return LL_RNG_IsActiveFlag_DRDY(RNGx);
		#endif /* CONFIG_SOC_SERIES_STM32WB0X */
		@@ -77,7 +94,11 @@ static inline uint32_t ll_rng_is_active_drdy(RNG_TypeDef *RNGx)
		static inline uint16_t ll_rng_read_rand_data(RNG_TypeDef *RNGx)
		{
		#if defined(CONFIG_SOC_SERIES_STM32WB0X)
		# if defined(CONFIG_SOC_STM32WB09XX)
		return (uint16_t)LL_RNG_GetRndVal(RNGx);
		# else
		return LL_RNG_ReadRandData16(RNGx);
		# endif
		#else
		return (uint16_t)LL_RNG_ReadRandData32(RNGx);
		#endif /* CONFIG_SOC_SERIES_STM32WB0X */

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