Commit 82bace6e authored by Francois Ramu's avatar Francois Ramu Committed by Carles Cufi
Browse files

tests: drivers: dma test on stm32f7 requires nocache memory 



Config the sram0 to be non-cachable to PASS the DMA testcases
chan_blen_transfer and loop_transfer
on the stm32f746zg and stm32f767zi nucleo boards.

The CONFIG_NOCACHE_MEMORY is useless as the memory region
gets the NOCACHE ATTRibutes for stm32H7 or stm32F7 as well.

Signed-off-by: default avatarFrancois Ramu <francois.ramu@st.com>
parent 800edb2b

tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.conf

+0 −1
Original line number Diff line number Diff line 
CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0

CONFIG_DMA_TRANSFER_CHANNEL_NR_1=1
 
CONFIG_NOCACHE_MEMORY=y

tests/drivers/dma/chan_blen_transfer/boards/nucleo_f746zg.overlay

+5 −0
Original line number Diff line number Diff line
@@ -5,3 +5,8 @@ 
 */



test_dma0: &dma2 { };



/* The test driver expects the SRAM0 region to be non-cachable */

&sram0 {

	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;

};

tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.conf

0 → 100644
+2 −0
Original line number Diff line number Diff line 
CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0

CONFIG_DMA_TRANSFER_CHANNEL_NR_1=1

tests/drivers/dma/chan_blen_transfer/boards/nucleo_f767zi.overlay

+5 −0
Original line number Diff line number Diff line
@@ -11,3 +11,8 @@ 
test_dma0: &dma2 {

	status = "okay";

};



/* The test driver expects the SRAM0 region to be non-cachable */

&sram0 {

	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;

};

tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.conf

+0 −3
Original line number Diff line number Diff line
@@ -7,6 +7,3 @@ CONFIG_DMA_LOOP_TRANSFER_NUMBER_OF_DMAS=2 
# has access to this section.

CONFIG_CODE_DATA_RELOCATION=y

CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM4"
 


# Required for SRAM4 to be non-cachable

CONFIG_NOCACHE_MEMORY=y

CRA Git | Maintained and supported by SUSTech CRA and CCSE