Commit 81b83902 authored by Quy Tran's avatar Quy Tran Committed by Anas Nashif
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soc: renesas: Add initial support for RA4E2 soc 



Initial commit to support Renesas RA4E2 SoC

Signed-off-by: default avatarQuy Tran <quy.tran.pz@renesas.com>
parent 9ea4cb96

dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi

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/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <zephyr/dt-bindings/clock/ra_clock.h>

#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>



/ {

	soc {

		sram0: memory@20000000 {

			compatible = "mmio-sram";

			reg = <0x20000000 DT_SIZE_K(40)>;

		};



		ioport8: gpio@40080100 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080100 0x20>;

			port = <8>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		flash-controller@407e0000 {

			reg = <0x407e0000 0x10000>;

			#address-cells = <1>;

			#size-cells = <1>;

			flash0: flash@0 {

				compatible = "soc-nv-flash";

				reg = <0x0 DT_SIZE_K(128)>;

			};

		};



		id_code: id_code@100a120 {

			compatible = "zephyr,memory-region";

			reg = <0x0100a120 0x10>;

			zephyr,memory-region = "ID_CODE";

			status = "okay";

		};

	};



	clocks: clocks {

		xtal: clock-xtal {

			compatible = "renesas,ra-cgc-external-clock";

			clock-frequency = <DT_FREQ_M(20)>;

			#clock-cells = <0>;

			status = "disabled";

		};



		hoco: clock-hoco {

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_M(20)>;

			#clock-cells = <0>;

		};



		moco: clock-moco {

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_M(8)>;

			#clock-cells = <0>;

		};



		loco: clock-loco {

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			#clock-cells = <0>;

		};



		subclk: clock-subclk {

			compatible = "renesas,ra-cgc-subclk";

			clock-frequency = <32768>;

			#clock-cells = <0>;

			status = "disabled";

		};



		pll: pll {

			compatible = "renesas,ra-cgc-pll";

			#clock-cells = <0>;



			/* PLL */

			source = <RA_PLL_SOURCE_MAIN_OSC>;

			div = <RA_PLL_DIV_1>;

			mul = <10 0>;

			freq = <DT_FREQ_M(200)>;

			status = "disabled";

		};



		pclkblock: pclkblock {

			compatible = "renesas,ra-cgc-pclk-block";

			#clock-cells = <0>;

			sysclock-src = <RA_CLOCK_SOURCE_PLL>;

			status = "okay";



			iclk: iclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclka: pclka {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkb: pclkb {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_4>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkc: pclkc {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_4>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkd: pclkd {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			fclk: fclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_4>;

				#clock-cells = <2>;

				status = "okay";

			};



			clkout: clkout {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};



			uclk: uclk {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};



			canfdclk: canfdclk {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};



			i3cclk: i3cclk {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};



			cecclk: cecclk {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};

		};

	};

};

dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi

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/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <mem.h>

#include <arm/armv8-m.dtsi>

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>

#include <freq.h>



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-m33";

			reg = <0>;

			#address-cells = <1>;

			#size-cells = <1>;



			mpu: mpu@e000ed90 {

				compatible = "arm,armv8m-mpu";

				reg = <0xe000ed90 0x40>;

			};

		};

	};



	soc {

		interrupt-parent = <&nvic>;



		system: system@4001e000 {

			compatible = "renesas,ra-system";

			reg = <0x4001e000 0x1000>;

			status = "okay";

		};



		flash-controller@407e0000 {

			reg = <0x407e0000 0x10000>;

			#address-cells = <1>;

			#size-cells = <1>;

		};



		ioport0: gpio@40080000 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080000 0x20>;

			port = <0>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport1: gpio@40080020 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080020 0x20>;

			port = <1>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport2: gpio@40080040 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080040 0x20>;

			port = <2>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport3: gpio@40080060 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080060 0x20>;

			port = <3>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport4: gpio@40080080 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080080 0x20>;

			port = <4>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport5: gpio@400800a0 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x400800a0 0x20>;

			port = <5>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		pinctrl: pin-controller@40080800 {

			compatible = "renesas,ra-pinctrl-pfs";

			reg = <0x40080800 0x3c0>;

			status = "okay";

		};



		sci0: sci0@40118000 {

			compatible = "renesas,ra-sci";

			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40118000 0x100>;

			clocks = <&pclka MSTPB 31>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <0>;

				status = "disabled";

			};

		};



		sci9: sci9@40118900 {

			compatible = "renesas,ra-sci";

			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40118900 0x100>;

			clocks = <&pclka MSTPB 22>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <9>;

				status = "disabled";

			};

		};



		option_setting_ofs: option_setting_ofs@100a100 {

			compatible = "zephyr,memory-region";

			reg = <0x0100a100 0x18>;

			zephyr,memory-region = "OPTION_SETTING_OFS";

			status = "okay";

		};



		option_setting_sas: option_setting_sas@100a134 {

			compatible = "zephyr,memory-region";

			reg = <0x0100a134 0xcc>;

			zephyr,memory-region = "OPTION_SETTING_SAS";

			status = "okay";

		};



		option_setting_s: option_setting_s@100a200 {

			compatible = "zephyr,memory-region";

			reg = <0x0100a200 0x100>;

			zephyr,memory-region = "OPTION_SETTING_S";

			status = "okay";

		};

	};

};



&nvic {

	arm,num-irq-priority-bits = <4>;

};

soc/renesas/ra/ra4e2/CMakeLists.txt

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# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



zephyr_include_directories(.)



zephyr_sources(

  soc.c

)



zephyr_linker_sources(SECTIONS sections.ld)



set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4e2/Kconfig

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# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



config SOC_SERIES_RA4E2

	select ARM

	select CPU_HAS_ARM_MPU

	select CPU_CORTEX_M33

	select HAS_RENESAS_RA_FSP

	select CPU_CORTEX_M_HAS_DWT

	select ARMV8_M_DSP

	select CPU_HAS_FPU

	select FPU

	select HAS_SWO

	select XIP

soc/renesas/ra/ra4e2/Kconfig.defconfig

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# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



if SOC_SERIES_RA4E2



config NUM_IRQS

	default 96



config PINCTRL

	default y



endif # SOC_SERIES_RA4E2

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