Commit 7f75e4f8 authored by Ryan QIAN's avatar Ryan QIAN Committed by Maureen Helm
Browse files

soc: arm: nxp_imx: rt: add device support i.MX RT1010 



- Add device support for i.MXRT1010

Signed-off-by: default avatarRyan QIAN <jianghao.qian@nxp.com>
parent df12b9ee

dts/arm/nxp/nxp_rt1010.dtsi

0 → 100644
+85 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2019, Linaro

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <nxp/nxp_rt.dtsi>



&sysclk {

	clock-frequency = <500000000>;

};



/* i.MX rt1010 default FlexRAM partition:

 * ITCM: 32KB

 * DTCM: 32KB

 * OCRAM: 64KB

 */

&itcm0 {

	reg = <0x00000000 0x8000>;

};



&dtcm0 {

	reg = <0x20000000 0x8000>;

};



&ocram0 {

	reg = <0x20200000 0x10000>;

};



&gpio1 {

	interrupts = <70 0>, <71 0>;

};



&gpio5 {

	interrupts = <73 0>;

};



&gpt1 {

	interrupts = <30 0>;

};



&gpt2 {

	interrupts = <31 0>;

};



&usbd1 {

	interrupts = <25 0>;

};



&flexspi0 {

	interrupts = <26 0>;

};



&flexpwm1_pwm0 {

	interrupts = <34 0>;

};



&flexpwm1_pwm1 {

	interrupts = <35 0>;

};



&flexpwm1_pwm2 {

	interrupts = <36 0>;

};



&flexpwm1_pwm3 {

	interrupts = <37 0>;

};



&flexpwm1 {

	interrupts = <38 0>;

};



/ {

	soc {

		gpio2_rt1010: gpio@42000000 {

			compatible = "nxp,imx-gpio";

			reg = <0x42000000 0x4000>;

			interrupts = <72 0>;

			label = "GPIO_2";

			gpio-controller;

			#gpio-cells = <2>;

		};

	};

};

soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010

0 → 100644
+35 −0
Original line number Diff line number Diff line 
# Kconfig - i.MX RT1010

#

# Copyright (c) 2019, NXP

#

# SPDX-License-Identifier: Apache-2.0

#



if SOC_MIMXRT1011



config SOC

	string

	default "mimxrt1011"



config HAS_ARM_DIV

	default n



config NUM_IRQS

	default 80



config ARM_DIV

	default 0



config AHB_DIV

	default 0



config IPG_DIV

	default 3



config GPIO

	default y



config FLEXSPI_CONFIG_BLOCK_OFFSET

	default 0x400



endif # SOC_MIMXRT1010

soc/arm/nxp_imx/rt/Kconfig.soc

+40 −0
Original line number Diff line number Diff line
@@ -7,6 +7,25 @@ choice 
	prompt "i.MX RT Selection"

	depends on SOC_SERIES_IMX_RT



config SOC_MIMXRT1011

	bool "SOC_MIMXRT1011"

	select HAS_MCUX

	select HAS_MCUX_CACHE

	select HAS_MCUX_CCM

	select HAS_MCUX_IGPIO

	select HAS_MCUX_LPI2C

	select HAS_MCUX_LPSPI

	select HAS_MCUX_LPUART

	select HAS_MCUX_GPT

	select HAS_MCUX_TRNG

	select CPU_HAS_ARM_MPU

	select INIT_SYS_PLL

	select INIT_USB1_PLL

	select INIT_ENET_PLL

	select HAS_MCUX_USB_EHCI

	select HAS_MCUX_USDHC1

	select HAS_MCUX_USDHC2



config SOC_MIMXRT1015

	bool "SOC_MIMXRT1015"

	select HAS_MCUX
@@ -170,6 +189,12 @@ endchoice 


if SOC_SERIES_IMX_RT



config SOC_PART_NUMBER_MIMXRT1011CAE4A

	bool



config SOC_PART_NUMBER_MIMXRT1011DAE5A

	bool



config SOC_PART_NUMBER_MIMXRT1015CAF4A

	bool
@@ -232,6 +257,8 @@ config SOC_PART_NUMBER_MIMXRT1064DVL6A 


config SOC_PART_NUMBER_IMX_RT

	string

	default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A

	default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A

	default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A

	default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A

	default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
@@ -276,6 +303,10 @@ config INIT_ENET_PLL 
	  MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection

	  for MIMXRT1021").



config HAS_ARM_DIV

	bool "Has the divider for ARM"

	default y



config ARM_DIV

	int "ARM clock divider"

	range 0 7
@@ -314,6 +345,15 @@ config BOOT_SEMC_NAND 


endchoice



config FLEXSPI_CONFIG_BLOCK_OFFSET

	hex "FlexSPI config block offset"

	default 0x0 if BOOT_FLEXSPI_NOR

	help

	  FlexSPI configuration block consists of parameters regarding specific

	  flash devices including read command sequence, quad mode enablement

	  sequence (optional), etc. The boot ROM expectes FlexSPI configuration

	  parameter to be presented in serail nor flash.



config IMAGE_VECTOR_TABLE_OFFSET

	hex "Image vector table offset"

	default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR

soc/arm/nxp_imx/rt/boot_header.ld

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
 * SPDX-License-Identifier: Apache-2.0

 */



. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;

KEEP(*(.boot_hdr.conf))

. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;

KEEP(*(.boot_hdr.ivt))

soc/arm/nxp_imx/rt/dts_fixup.h

+7 −0
Original line number Diff line number Diff line
@@ -20,12 +20,19 @@ 
#define DT_MCUX_IGPIO_1_IRQ_1			DT_NXP_IMX_GPIO_401B8000_IRQ_1

#define DT_MCUX_IGPIO_1_IRQ_1_PRI		DT_NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY



#ifdef CONFIG_SOC_MIMXRT1011

#define DT_MCUX_IGPIO_2_BASE_ADDRESS	DT_NXP_IMX_GPIO_42000000_BASE_ADDRESS

#define DT_MCUX_IGPIO_2_NAME			DT_NXP_IMX_GPIO_42000000_LABEL

#define DT_MCUX_IGPIO_2_IRQ_0			DT_NXP_IMX_GPIO_42000000_IRQ_0

#define DT_MCUX_IGPIO_2_IRQ_0_PRI	DT_NXP_IMX_GPIO_42000000_IRQ_0_PRIORITY

#else

#define DT_MCUX_IGPIO_2_BASE_ADDRESS		DT_NXP_IMX_GPIO_401BC000_BASE_ADDRESS

#define DT_MCUX_IGPIO_2_NAME			DT_NXP_IMX_GPIO_401BC000_LABEL

#define DT_MCUX_IGPIO_2_IRQ_0			DT_NXP_IMX_GPIO_401BC000_IRQ_0

#define DT_MCUX_IGPIO_2_IRQ_0_PRI		DT_NXP_IMX_GPIO_401BC000_IRQ_0_PRIORITY

#define DT_MCUX_IGPIO_2_IRQ_1			DT_NXP_IMX_GPIO_401BC000_IRQ_1

#define DT_MCUX_IGPIO_2_IRQ_1_PRI		DT_NXP_IMX_GPIO_401BC000_IRQ_1_PRIORITY

#endif



#define DT_MCUX_IGPIO_3_BASE_ADDRESS		DT_NXP_IMX_GPIO_401C0000_BASE_ADDRESS

#define DT_MCUX_IGPIO_3_NAME			DT_NXP_IMX_GPIO_401C0000_LABEL

CRA Git | Maintained and supported by SUSTech CRA and CCSE