soc: riscv32: miv: soc.h: use defines from device tree (6fcfb837) · Commits · Wenxi XU / zephyr

Use values generated from the device tree in RISCV_ROM_BASE, RISCV_ROM_SIZE, RISCV_RAM_BASE, RISCV_RAM_SIZE macros. Signed-off-by:

soc/riscv32/riscv-privilege/miv/soc.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -5,6 +5,7 @@
		#define __RISCV32_MIV_SOC_H_

		#include <soc_common.h>
		#include <generated_dts_board.h>

		/* GPIO Interrupts */
		#define MIV_GPIO_0_IRQ (RISCV_MAX_GENERIC_IRQ + 0)
		@@ -54,7 +55,7 @@
		#define RISCV_MTIMECMP_BASE 0x44004000

		/* lib-c hooks required RAM defined variables */
		#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
		#define RISCV_RAM_SIZE CONFIG_RISCV_RAM_SIZE
		#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS
		#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE)

		#endif /* __RISCV32_MIV_SOC_H_ */