Commit 6e7f50d7 authored by Najumon B.A's avatar Najumon B.A Committed by Carles Cufi
Browse files

docs: rename intel,pcie compatible id to pcie-controller 



rename intel,pcie compatible id referance to pcie-controller in
header file comments and rst files

Signed-off-by: default avatarNajumon B.A <najumon.ba@intel.com>
parent 359e5839

doc/services/storage/disk/nvme.rst

+0 −5
Original line number Diff line number Diff line
@@ -43,11 +43,6 @@ Any board exposing an NVMe disk should provide a DTS overlay to enable its use w 
    #include <zephyr/dt-bindings/pcie/pcie.h>

    / {

        pcie0 {

            #address-cells = <1>;

            #size-cells = <1>;

            compatible = "intel,pcie";

            ranges;



            nvme0: nvme0 {

                compatible = "nvme-controller";

                vendor-id = <VENDOR_ID>;

include/zephyr/devicetree.h

+7 −7
Original line number Diff line number Diff line
@@ -1612,7 +1612,7 @@ 
 *

 * @code{.dts}

 *     pcie0: pcie@0 {

 *             compatible = "intel,pcie";

 *             compatible = "pcie-controller";

 *             reg = <0 1>;

 *             #address-cells = <3>;

 *             #size-cells = <2>;
@@ -1657,7 +1657,7 @@ 
 *

 * @code{.dts}

 *     pcie0: pcie@0 {

 *             compatible = "intel,pcie";

 *             compatible = "pcie-controller";

 *             reg = <0 1>;

 *             #address-cells = <3>;

 *             #size-cells = <2>;
@@ -1711,7 +1711,7 @@ 
 *             #address-cells = <2>;

 *

 *             pcie0: pcie@0 {

 *                     compatible = "intel,pcie";

 *                     compatible = "pcie-controller";

 *                     reg = <0 0 1>;

 *                     #address-cells = <3>;

 *                     #size-cells = <2>;
@@ -1764,7 +1764,7 @@ 
 *             #address-cells = <2>;

 *

 *             pcie0: pcie@0 {

 *                     compatible = "intel,pcie";

 *                     compatible = "pcie-controller";

 *                     reg = <0 0 1>;

 *                     #address-cells = <3>;

 *                     #size-cells = <2>;
@@ -1804,7 +1804,7 @@ 
 *             #address-cells = <2>;

 *

 *             pcie0: pcie@0 {

 *                     compatible = "intel,pcie";

 *                     compatible = "pcie-controller";

 *                     reg = <0 0 1>;

 *                     #address-cells = <3>;

 *                     #size-cells = <2>;
@@ -1853,7 +1853,7 @@ 
 *             #address-cells = <2>;

 *

 *             pcie0: pcie@0 {

 *                     compatible = "intel,pcie";

 *                     compatible = "pcie-controller";

 *                     reg = <0 0 1>;

 *                     #address-cells = <3>;

 *                     #size-cells = <2>;
@@ -1902,7 +1902,7 @@ 
 *             #address-cells = <2>;

 *

 *             pcie0: pcie@0 {

 *                     compatible = "intel,pcie";

 *                     compatible = "pcie-controller";

 *                     reg = <0 0 1>;

 *                     #address-cells = <3>;

 *                     #size-cells = <2>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE