Commit 6e6403d4 authored by Quy Tran's avatar Quy Tran Committed by Anas Nashif
Browse files

soc: renesas: Add initial support for RA4W1 SOC 

Initial commit to support Renesas RA4W1 SOC

Signed-off-by: default avatarQuy Tran <quy.tran.pz@renesas.com>
parent d95ebf90

dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi

0 → 100644
+146 −0
Changes for dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi: 146 added lines, 0 removed lines.
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <zephyr/dt-bindings/clock/ra_clock.h>

#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>



/ {

	soc {

		sram0: memory@20000000 {

			compatible = "mmio-sram";

			reg = <0x20000000 DT_SIZE_K(96)>;

		};



		flash-controller@407e0000 {

			flash0: flash@0 {

				compatible = "soc-nv-flash";

				reg = <0x0 DT_SIZE_K(512)>;

			};

		};



		sci4: sci4@40070080  {

			compatible = "renesas,ra-sci";

			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40070080 0x20>;

			clocks = <&pclka MSTPB 26>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <4>;

				status = "disabled";

			};

		};

	};



	clocks: clocks {

		xtal: clock-xtal {

			compatible = "renesas,ra-cgc-external-clock";

			clock-frequency = <DT_FREQ_M(8)>;

			#clock-cells = <0>;

			status = "disabled";

		};



		hoco: clock-hoco {

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_M(48)>;

			#clock-cells = <0>;

		};



		moco: clock-moco {

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_M(8)>;

			#clock-cells = <0>;

		};



		loco: clock-loco {

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			#clock-cells = <0>;

		};



		subclk: clock-subclk {

			compatible = "renesas,ra-cgc-subclk";

			clock-frequency = <32768>;

			#clock-cells = <0>;

			status = "disabled";

		};



		pll: pll {

			compatible = "renesas,ra-cgc-pll";

			#clock-cells = <0>;



			/* PLL */

			source = <RA_PLL_SOURCE_MAIN_OSC>;

			div = <RA_PLL_DIV_2>;

			mul = <12 0>;

			freq = <DT_FREQ_M(48)>;

			status = "disabled";

		};



		pclkblock: pclkblock {

			compatible = "renesas,ra-cgc-pclk-block";

			#clock-cells = <0>;

			sysclock-src = <RA_CLOCK_SOURCE_HOCO>;

			status = "okay";



			iclk: iclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_1>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclka: pclka {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_1>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkb: pclkb {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkc: pclkc {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_1>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkd: pclkd {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_1>;

				#clock-cells = <2>;

				status = "okay";

			};



			fclk: fclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			clkout: clkout {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};



			uclk: uclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_USB_CLOCK_DIV_1>;

				#clock-cells = <2>;

				status = "okay";

			};

		};

	};

};

dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi

0 → 100644
+174 −0
Changes for dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi: 174 added lines, 0 removed lines.
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <mem.h>

#include <arm/armv7-m.dtsi>

#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>

#include <freq.h>



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-m4";

			reg = <0>;

			#address-cells = <1>;

			#size-cells = <1>;



			mpu: mpu@e000ed90 {

				compatible = "arm,armv7m-mpu";

				reg = <0xe000ed90 0x40>;

			};



		};

	};



	soc {

		system: system@4001e000 {

			compatible = "renesas,ra-system";

			reg = <0x4001e000 0x1000>;

			status = "okay";

		};



		flash-controller@407e0000 {

			reg = <0x407e0000 0x10000>;

			#address-cells = <1>;

			#size-cells = <1>;

		};



		ioport0: gpio@40040000 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40040000 0x20>;

			port = <0>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport1: gpio@40040020 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40040020 0x20>;

			port = <1>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport2: gpio@40040040 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40040040 0x20>;

			port = <2>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport3: gpio@40040060 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40040060 0x20>;

			port = <3>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport4: gpio@40040080 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40040080 0x20>;

			port = <4>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport5: gpio@400400a0 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x400400a0 0x20>;

			port = <5>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport9: gpio@40040120 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40040120 0x20>;

			port = <9>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		pinctrl: pin-controller@40040800 {

			compatible = "renesas,ra-pinctrl-pfs";

			reg = <0x40040800 0x3c0>;

			status = "okay";

		};



		sci0: sci0@40070000  {

			compatible = "renesas,ra-sci";

			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40070000 0x20>;

			clocks = <&pclka MSTPB 31>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <0>;

				status = "disabled";

			};

		};



		sci1: sci1@40070020  {

			compatible = "renesas,ra-sci";

			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40070020 0x20>;

			clocks = <&pclka MSTPB 30>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <1>;

				status = "disabled";

			};

		};



		sci9: sci9@40070120  {

			compatible = "renesas,ra-sci";

			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40070120 0x20>;

			clocks = <&pclka MSTPB 22>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <9>;

				status = "disabled";

			};

		};



		id_code: id_code@1010018 {

			compatible = "zephyr,memory-region";

			reg = <0x01010018 0x20>;

			zephyr,memory-region = "ID_CODE";

			status = "okay";

		};

	};

};



&nvic {

	arm,num-irq-priority-bits = <4>;

};

soc/renesas/ra/ra4w1/CMakeLists.txt

0 → 100644
+14 −0
Changes for soc/renesas/ra/ra4w1/CMakeLists.txt: 14 added lines, 0 removed lines.
Original line number Diff line number Diff line 
# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



zephyr_include_directories(.)



zephyr_sources(

  soc.c

)



zephyr_linker_sources(ROM_START opt_set_mem.ld)



zephyr_linker_sources(SECTIONS sections.ld)



set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4w1/Kconfig

0 → 100644
+13 −0
Changes for soc/renesas/ra/ra4w1/Kconfig: 13 added lines, 0 removed lines.
Original line number Diff line number Diff line 
# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



config SOC_SERIES_RA4W1

	select ARM

	select CPU_HAS_ARM_MPU

	select CPU_CORTEX_M4

	select HAS_RENESAS_RA_FSP

	select CPU_CORTEX_M_HAS_DWT

	select CPU_HAS_FPU

	select FPU

	select HAS_SWO

	select XIP

soc/renesas/ra/ra4w1/Kconfig.defconfig

0 → 100644
+12 −0
Changes for soc/renesas/ra/ra4w1/Kconfig.defconfig: 12 added lines, 0 removed lines.
Original line number Diff line number Diff line 
# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



if SOC_SERIES_RA4W1



config NUM_IRQS

	default 32



config PINCTRL

	default y



endif # SOC_SERIES_RA4W1

CRA Git | Maintained and supported by SUSTech CRA and CCSE