Commit 682b5724 authored by Daniel Leung's avatar Daniel Leung Committed by Anas Nashif
Browse files

xtensa: remove ZSR_MMU_0 and ZSR_MMU_1 



They are not being used in the code so there is no need to
reserve them as scratch registers.

Signed-off-by: default avatarDaniel Leung <daniel.leung@intel.com>
parent 3dabe035

arch/xtensa/core/gen_zsr.py

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ args = parse_args() 


NEEDED = ["A0SAVE", "CPU"]

if args.mmu:

    NEEDED += ["MMU_0", "MMU_1", "DBLEXC"]

    NEEDED += ["DBLEXC"]

if args.coherence:

    NEEDED += ["FLUSH"]

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