Commit 63c24d9d authored by Henrik Brix Andersen's avatar Henrik Brix Andersen Committed by Benjamin Cabé
Browse files

soc: neorv32: update to support NEORV32 v1.11.1 

Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32
v1.11.1. Notable changes include:

- Optional RISC-V ISA Kconfigs are now selected on the board level.
- Peripheral registers are now automatically reset in hardware, no need for
  software initialization code.
- The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt
  support will be submitted in a separate PR.
- Default board configuration has 64k RAM and is clocked at 18 MHz.

Signed-off-by: default avatarHenrik Brix Andersen <henrik@brixandersen.dk>
parent 4899cc10

boards/others/neorv32/CMakeLists.txt

+2 −2
Changes for boards/others/neorv32/CMakeLists.txt: 2 added lines, 2 removed lines.
Original line number Diff line number Diff line 
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>

# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>

# SPDX-License-Identifier: Apache-2.0



if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN))
@@ -18,7 +18,7 @@ if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN)) 


    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands

      COMMAND ${IMAGE_GEN}

      ARGS -app_img

      ARGS -app_vhd

      ${CONFIG_KERNEL_BIN_NAME}.bin

      ${CONFIG_KERNEL_BIN_NAME}.vhd

      ${PROJECT_BINARY_DIR}

boards/others/neorv32/Kconfig

0 → 100644
+7 −0
Changes for boards/others/neorv32/Kconfig: 7 added lines, 0 removed lines.
Original line number Diff line number Diff line 
# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>

# SPDX-License-Identifier: Apache-2.0



config BOARD_NEORV32

	select RISCV_ISA_RV32I

	select RISCV_ISA_EXT_M

	select ATOMIC_OPERATIONS_C

boards/others/neorv32/doc/index.rst

+11 −10
Changes for boards/others/neorv32/doc/index.rst: 11 added lines, 10 removed lines.
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ For more information about the NEORV32, see the following websites: 
- `The NEORV32 RISC-V Processor Datasheet`_

- `The NEORV32 RISC-V Processor User Guide`_



The currently supported version is 1.8.6.

The currently supported version is NEORV32 v1.11.1.



Supported Features

==================
@@ -27,7 +27,7 @@ using :ref:`devicetree overlays <use-dt-overlays>`. 
System Clock

============



The default board configuration assumes a system clock of 100 MHz. The clock

The default board configuration assumes a system clock of 18 MHz. The clock

frequency can be overridden by changing the ``clock-frequency`` property of the

``cpu0`` devicetree node.
@@ -37,9 +37,10 @@ CPU 
The default board configuration assumes the NEORV32 CPU implementation has the

following RISC-V ISA extensions enabled:



- C (Compresses Instructions)

- I (Base Integer Instruction Set, 32-bit)

- M (Integer Multiplication and Division)

- Zicsr (Control and Status Register (CSR) Instructions)

- Zicsr (Control and Status Register (CSR) Instructions, always enabled)

- Zifencei (Instruction-fetch fence, always enabled)



Internal Instruction Memory

===========================
@@ -52,7 +53,7 @@ instruction memory can be overridden by changing the ``reg`` property of the 
Internal Data Memory

====================



The default board configuration assumes the NEORV32 SoC implementation has a 32k

The default board configuration assumes the NEORV32 SoC implementation has a 64k

byte internal data memory (DMEM). The size of the data memory can be overridden

by changing the ``reg`` property of the ``dmem`` devicetree node.
@@ -115,21 +116,21 @@ implementation with the On-Chip Debugger (OCD) and bootloader enabled. 


The default board configuration uses an :ref:`openocd-debug-host-tools`

configuration similar to the example provided by the NEORV32 project. Other

JTAGs can be used by providing further arguments when building. Here is an

example for using the Flyswatter JTAG:

JTAGs can be used by providing further arguments when flashing. Here is an

example for using the Flyswatter JTAG @ 2 kHz:



.. zephyr-app-commands::

   :zephyr-app: samples/hello_world

   :board: neorv32

   :goals: flash

   :gen-args: -DBOARD_RUNNER_ARGS_openocd="--config;interface/ftdi/flyswatter.cfg;--config;neorv32.cfg;--cmd-pre-init;'adapter speed 2000'"

   :flash-args: --config interface/ftdi/flyswatter.cfg --config neorv32.cfg --cmd-pre-init 'adapter speed 2000'



After flashing, you should see message similar to the following in the terminal:



.. code-block:: console



   *** Booting Zephyr OS build zephyr-vn.n.nn  ***

   Hello World! neorv32

   Hello World! neorv32/neorv32



Note, however, that the application was not persisted in flash memory by the

above steps. It was merely written to internal block RAM in the FPGA. It will
@@ -176,7 +177,7 @@ similar to the following in the terminal: 
.. code-block:: console



   *** Booting Zephyr OS build zephyr-vn.n.nn  ***

   Hello World! neorv32

   Hello World! neorv32/neorv32



.. _The NEORV32 RISC-V Processor GitHub:

   https://github.com/stnolting/neorv32

boards/others/neorv32/neorv32.dts

+26 −23
Changes for boards/others/neorv32/neorv32.dts: 26 added lines, 23 removed lines.
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>

 * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>

 *

 * SPDX-License-Identifier: Apache-2.0

 */
@@ -29,25 +29,9 @@ 
		zephyr,uart-pipe = &uart0;

	};



	soc {

		imem: memory@0 {

			compatible = "soc-nv-flash", "mmio-sram";

			reg = <0x0 DT_SIZE_K(64)>;

		};



		bootrom: memory@ffff0000 {

			compatible = "soc-nv-flash", "mmio-sram";

			reg = <0xffff0000 DT_SIZE_K(4)>;

		};



		dmem: memory@80000000 {

			compatible = "mmio-sram";

			reg = <0x80000000 DT_SIZE_K(32)>;

		};

	};



	leds {

		compatible = "gpio-leds";



		led0: led0 {

			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;

			label = "LED_0";
@@ -71,18 +55,37 @@ 
};



&cpu0 {

	clock-frequency = <DT_FREQ_M(100)>;

	riscv,isa = "rv32im_zicsr_zifencei";

	clock-frequency = <DT_FREQ_M(18)>;

};



&uart0 {

&bootrom {

	status = "okay";

	current-speed = <19200>;

};



&gpio_lo {

&imem {

	status = "okay";

	reg = <0x0 DT_SIZE_K(64)>;

};



&dmem {

	status = "okay";

	reg = <0x80000000 DT_SIZE_K(64)>;

};



&clint {

	status = "okay";

};



&mtimer {

	status = "okay";

};



&uart0 {

	status = "okay";

	current-speed = <19200>;

};



&gpio_hi {

&gpio {

	status = "okay";

};

boards/others/neorv32/neorv32.yaml

+1 −1
Changes for boards/others/neorv32/neorv32.yaml: 1 added line, 1 removed line.
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ arch: riscv 
toolchain:

  - cross-compile

  - zephyr

ram: 32

ram: 64

flash: 64

supported:

  - gpio

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