Commit 61720927 authored by Nazar Palamar's avatar Nazar Palamar Committed by Anas Nashif
Browse files

test: arm: irq: Add overlays files for Infineon boards

Changed interrupt priority for GPIO, default 6 is not suitable for
for the ZERO_LATENCY_IRQS function used in this test.
used in this test.

Signed-off-by: default avatarNazar Palamar <nazar.palamar@infineon.com>
parent 697efe8b
Loading
Loading
Loading
Loading
+37 −0
Changes for tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_062_4343w.overlay: 37 added lines, 0 removed lines.
Original line number Diff line number Diff line
/*
 * Copyright (c) 2024 Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 */

/* Changed default interrupts priority for GPIO to 4 */
&gpio_prt0 {
	interrupts = <0 4>;
};

&gpio_prt2 {
	interrupts = <2 4>;
};

&gpio_prt3 {
	interrupts = <3 4>;
};

&gpio_prt5 {
	interrupts = <5 4>;
};

&gpio_prt6 {
	interrupts = <6 4>;
};

&gpio_prt9 {
	interrupts = <9 4>;
};

&gpio_prt12 {
	interrupts = <12 4>;
};

&gpio_prt13 {
	interrupts = <13 4>;
};
+33 −0
Changes for tests/arch/arm/arm_irq_advanced_features/boards/cy8cproto_063_ble.overlay: 33 added lines, 0 removed lines.
Original line number Diff line number Diff line
/*
 * Copyright (c) 2024 Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 */

/* Changed default interrupts priority for GPIO to 4 */
&gpio_prt0 {
	interrupts = <0 4>;
};

&gpio_prt5 {
	interrupts = <5 4>;
};

&gpio_prt6 {
	interrupts = <6 4>;
};

&gpio_prt7 {
	interrupts = <7 4>;
};

&gpio_prt9 {
	interrupts = <9 4>;
};

&gpio_prt10 {
	interrupts = <10 4>;
};

&gpio_prt12 {
	interrupts = <12 4>;
};
+21 −0
Changes for tests/arch/arm/arm_irq_advanced_features/boards/cyw920829m2evk_02.overlay: 21 added lines, 0 removed lines.
Original line number Diff line number Diff line
/*
 * Copyright (c) 2024 Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 */

/* Changed default interrupts priority for GPIO to 4 */
&gpio_prt0 {
	interrupts = <0 4>;
};

&gpio_prt1 {
	interrupts = <1 4>;
};

&gpio_prt3 {
	interrupts = <3 4>;
};

&gpio_prt5 {
	interrupts = <5 4>;
};
+37 −0
Changes for tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_062_4343w.overlay: 37 added lines, 0 removed lines.
Original line number Diff line number Diff line
/*
 * Copyright (c) 2024 Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 */

/* Changed default interrupts priority for GPIO to 4 */
&gpio_prt0 {
	interrupts = <0 4>;
};

&gpio_prt2 {
	interrupts = <2 4>;
};

&gpio_prt3 {
	interrupts = <3 4>;
};

&gpio_prt5 {
	interrupts = <5 4>;
};

&gpio_prt6 {
	interrupts = <6 4>;
};

&gpio_prt9 {
	interrupts = <9 4>;
};

&gpio_prt12 {
	interrupts = <12 4>;
};

&gpio_prt13 {
	interrupts = <13 4>;
};
+33 −0
Changes for tests/arch/arm/arm_irq_zero_latency_levels/boards/cy8cproto_063_ble.overlay: 33 added lines, 0 removed lines.
Original line number Diff line number Diff line
/*
 * Copyright (c) 2024 Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 */

/* Changed default interrupts priority for GPIO to 4 */
&gpio_prt0 {
	interrupts = <0 4>;
};

&gpio_prt5 {
	interrupts = <5 4>;
};

&gpio_prt6 {
	interrupts = <6 4>;
};

&gpio_prt7 {
	interrupts = <7 4>;
};

&gpio_prt9 {
	interrupts = <9 4>;
};

&gpio_prt10 {
	interrupts = <10 4>;
};

&gpio_prt12 {
	interrupts = <12 4>;
};
Loading