Commit 60cd83e6 authored by Sylvio Alves's avatar Sylvio Alves Committed by Daniel DeGrasse
Browse files

clock: esp32c6: enable and calibrate digital regulators 

Enable the RTC-domain and main digital regulators early in clock init,
then load and program the factory/runtime calibrated bias values for
high-power and low-power regulators into the PMU. This ensures the
correct voltage/current settings for stable, low-noise clock operation
in active, modem and sleep modes.

Signed-off-by: default avatarSylvio Alves <sylvio.alves@espressif.com>
parent 061036f9

drivers/clock_control/clock_control_esp32.c

+16 −0
Changes for drivers/clock_control/clock_control_esp32.c: 16 added lines, 0 removed lines.
Original line number Diff line number Diff line
@@ -646,6 +646,19 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf 
	REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq);

	REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);

	REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq);

	REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);

	REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);



	uint32_t hp_cali_dbias = get_act_hp_dbias();

	uint32_t lp_cali_dbias = get_act_lp_dbias();



	SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS,

			  hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);

	SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS,

			  hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);

	SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS,

			  lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);



#else

	REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);

	REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
@@ -655,6 +668,9 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf 
	REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1);

#elif defined(CONFIG_SOC_SERIES_ESP32C6)

	clk_ll_rc_fast_tick_conf();



	esp_rom_uart_tx_wait_idle(0);

	rtc_clk_xtal_freq_update(rtc_clk_cfg.xtal_freq);

#else

	/* Configure 150k clock division */

	rtc_clk_divider_set(rtc_clk_cfg.clk_rtc_clk_div);

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