Commit 5917ab90 authored by Jay Vasanth's avatar Jay Vasanth Committed by Carles Cufi
Browse files

dts: Update MEC172x pinctrl dts 



Update dtsi and dts bindings for pinctrl driver

Signed-off-by: default avatarJay Vasanth <jay.vasanth@microchip.com>
parent 2cd02bd8

boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts

+58 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
/dts-v1/;



#include <microchip/mec172xnsz.dtsi>

#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>



/ {

	model = "Microchip MEC172XEVB_ASSY6906 evaluation board";
@@ -76,14 +77,24 @@ 
&uart1 {

	status = "okay";

	current-speed = <115200>;

	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;

	pinctrl-names = "default";

};



&adc0 {

	status = "okay";

	pinctrl-0 = <&adc00_gpio200 &adc03_gpio203

		     &adc04_gpio204 &adc05_gpio205>;

	pinctrl-names = "default";

};



&espi0 {

	status = "okay";

	pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066

		      &espi_alert_n_gpio063 &espi_clk_gpio065

		      &espi_io0_gpio070 &espi_io1_gpio071

		      &espi_io2_gpio072 &espi_io3_gpio073 >;

	pinctrl-names = "default";

};



/* enable various eSPI child devices (host facing) */
@@ -107,11 +118,15 @@ 
	status = "okay";

};



/* I2C */

&i2c_smb_0 {

	status = "okay";

	label = "I2C0";

	port_sel = <0>;



	pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;

	pinctrl-names = "default";



	pca9555@26 {

		compatible = "nxp,pca95xx";

		label = "GPIO_P0";
@@ -130,16 +145,50 @@ 
	};

};



&i2c00_scl_gpio004 {

	drive-open-drain;

	output-high;

};



&i2c00_sda_gpio003 {

	drive-open-drain;

	output-high;

};



&i2c_smb_1 {

	status = "okay";

	label = "I2C1";

	port_sel = <1>;

	pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;

	pinctrl-names = "default";

};



&i2c01_scl_gpio131 {

	drive-open-drain;

	output-high;

};



&i2c01_sda_gpio130 {

	drive-open-drain;

	output-high;

};



&i2c_smb_2 {

	status = "okay";

	label = "I2C7";

	port_sel = <7>;

	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;

	pinctrl-names = "default";

};



&i2c07_scl_gpio013 {

	drive-open-drain;

	output-high;

};



&i2c07_sda_gpio012 {

	drive-open-drain;

	output-high;

};



&spi0 {
@@ -147,6 +196,15 @@ 
	clock-frequency = <4000000>;

	lines = <4>;

	chip-select = <0>;

	port-sel = <0>; /* Shared SPI */



	pinctrl-0 = < &shd_cs0_n_gpio055

		      &shd_clk_gpio056

		      &shd_io0_gpio223

		      &shd_io1_gpio224

		      &shd_io2_gpio227

		      &shd_io3_gpio016 >;

	pinctrl-names = "default";

};



&kscan0 {

dts/arm/microchip/mec172x/mec172xnsz-pinctrl.dtsi

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File added.

Preview size limit exceeded, changes collapsed.

dts/arm/microchip/mec172xnsz.dtsi

+72 −65
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@@ -287,6 +287,12 @@ 
				status = "disabled";

			};

		};

		pinctrl: pin-controller@40081000 {

			compatible = "microchip,xec-pinctrl";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x40081000 0x1000>;



			gpio_000_036: gpio@40081000 {

				compatible = "microchip,xec-gpio-v2";

				reg = < 0x40081000 0x80 0x40081300 0x04
@@ -353,6 +359,7 @@ 
				girq-id = <26>;

				#gpio-cells=<2>;

			};

		};

		wdog: watchdog@40000400 {

			compatible = "microchip,xec-watchdog";

			reg = <0x40000400 0x400>;

dts/bindings/pinctrl/microchip,xec-pinctrl.yaml

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# Copyright (c) 2020 Linaro Limited

# Copyright (c) 2021 Microchip Technology Inc.

# SPDX-License-Identifier: Apache-2.0



description: |

    Microchip XEC Pin controller Node

    Based on pincfg-node.yaml binding.

    The MCHP XEC pin controller is a singleton node responsible for controlling

    pin function selection and pin properties. For example, you can use this

    node to select peripheral pin functions.



    The node has the 'pinctrl' node label set in your SoC's devicetree,

    so you can modify it like this:



      &pinctrl {

              /* your modifications go here */

      };



    All device pin configurations should be placed in child nodes of the

    'pinctrl' node, as in the spi0 example shown at the end:



    A group can also specify shared pin properties common to all the specified

    pins, such as the 'bias-pull-up' property in group 2. Here is a list of

    supported standard pin properties:



    - bias-disable: Disable pull-up/down (default behavior, not required).

    - bias-pull-down: Enable pull-down resistor.

    - bias-pull-up: Enable pull-up resistor.

    - drive-push-pull: Output driver is push-pull (default, not required).

    - drive-open-drain: Output driver is open-drain.

    - output-high: Set output state high when pin configured.

    - output-low: Set output state low when pin configured.



    Custom pin properties for drive strength and slew rate are available:

    - drive-strength

    - slew-rate



    Driver strength and slew rate hardware defaults vary by SoC and pin.



    An example for MEC172x family, include the chip level pinctrl

    DTSI file in the board level DTS:



      #include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>



    We want to use the shared SPI port of the MEC172x QMSPI controller

    and want the chip select 0 to be open-drain.



    To change a pin's pinctrl default properties add a reference to the

    pin in the board's DTS file and set the properties.



      &spi0 {

        pinctrl-0 = < &shd_cs0_n_gpio055

                      &shd_clk_gpio056

                      &shd_io0_gpio223

                      &shd_io1_gpio224

                      &shd_io3_gpio016 >;

        pinctrl-names = "default";

      }



      &shd_cs0_n_gpio055 {

        drive-open-drain;

      };



compatible: "microchip,xec-pinctrl"



include:

    - name: base.yaml

    - name: pincfg-node.yaml

      child-binding:

        property-allowlist:

          - bias-disable

          - bias-pull-down

          - bias-pull-up

          - drive-push-pull

          - drive-open-drain

          - low-power-enable

          - output-high

          - output-low



properties:

    reg:

      required: true



child-binding:

    description: |

      This binding gives a base representation of the Microchip XEC pins

      configuration



    properties:

        pinmux:

            type: int

            required: true

            description: Pinmux selection



        slew-rate:

          required: false

          type: string

          default: "low-speed"

          enum:

          - "low-speed"

          - "high-speed"

          description: |

            Pin speed. The default value of slew-rate is the SoC power-on-reset

            value. Please refer to the data sheet as a small number of pins

            may have a different default and some pins do not implement

            slew rate adjustment.



        drive-strength:

          required: false

          type: string

          default: "1x"

          enum:

            - "1x"

            - "2x"

            - "4x"

            - "6x"

          description: |

            Pin output drive strength for PIO and PIO-24 pin types. Default

            is "1x" for most pins. PIO pins are 2, 4, 8, or 12 mA. PIO-24 pins

            are 4, 8, 16, or 24 mA. Please refer to the data sheet for each

            pin's PIO type and default drive strength.

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