Commit 57723cf4 authored by Hubert Guan's avatar Hubert Guan Committed by Carles Cufi
Browse files

dts: arm: st: Refactor DTSI files to use macro 



Replaces raw hex codes by using STM32_CLOCK macro

Signed-off-by: default avatarHubert Guan <hguan@ucsb.edu>
parent 79cf84c6

dts/arm/st/c0/stm32c0.dtsi

+17 −17
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ 
			compatible = "st,stm32-flash-controller";

			reg = <0x40022000 0x400>;

			interrupts = <3 0>;

			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;

			clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;



			#address-cells = <1>;

			#size-cells = <1>;
@@ -133,7 +133,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x50000000 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;

				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;

			};



			gpiob: gpio@50000400 {
@@ -141,7 +141,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x50000400 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;

				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;

			};



			gpioc: gpio@50000800 {
@@ -149,7 +149,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x50000800 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;

				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;

			};



			gpiof: gpio@50001400 {
@@ -157,7 +157,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x50001400 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;

				clocks = <&rcc STM32_CLOCK(IOP, 5U)>;

			};

		};
@@ -165,7 +165,7 @@ 
			compatible = "st,stm32-rtc";

			reg = <0x40002800 0x400>;

			interrupts = <2 0>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;

			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;

			prescaler = <32768>;

			alarms-count = <1>;

			alrm-exti-line = <19>;
@@ -175,7 +175,7 @@ 
		wwdg: watchdog@40002c00 {

			compatible = "st,stm32-window-watchdog";

			reg = <0x40002C00 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;

			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;

			interrupts = <0 2>;

			status = "disabled";

		};
@@ -189,7 +189,7 @@ 
		usart1: serial@40013800 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40013800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;

			clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;

			resets = <&rctl STM32_RESET(APB1H, 14U)>;

			interrupts = <27 0>;

			status = "disabled";
@@ -198,7 +198,7 @@ 
		usart2: serial@40004400 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40004400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;

			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;

			resets = <&rctl STM32_RESET(APB1L, 17U)>;

			interrupts = <28 0>;

			status = "disabled";
@@ -207,7 +207,7 @@ 
		timers1: timers@40012c00 {

			compatible = "st,stm32-timers";

			reg = <0x40012C00 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;

			clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>;

			resets = <&rctl STM32_RESET(APB1H, 11U)>;

			interrupts = <13 0>, <14 0>;

			interrupt-names = "brk_up_trg_com", "cc";
@@ -224,7 +224,7 @@ 
		timers3: timers@40000400 {

			compatible = "st,stm32-timers";

			reg = <0x40000400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;

			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;

			resets = <&rctl STM32_RESET(APB1L, 1U)>;

			interrupts = <16 0>;

			interrupt-names = "global";
@@ -241,7 +241,7 @@ 
		timers14: timers@40002000 {

			compatible = "st,stm32-timers";

			reg = <0x40002000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;

			clocks = <&rcc STM32_CLOCK(APB1_2, 15U)>;

			resets = <&rctl STM32_RESET(APB1H, 15U)>;

			interrupts = <19 0>;

			interrupt-names = "global";
@@ -258,7 +258,7 @@ 
		timers16: timers@40014400 {

			compatible = "st,stm32-timers";

			reg = <0x40014400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;

			clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>;

			resets = <&rctl STM32_RESET(APB1H, 17U)>;

			interrupts = <21 0>;

			interrupt-names = "global";
@@ -275,7 +275,7 @@ 
		timers17: timers@40014800 {

			compatible = "st,stm32-timers";

			reg = <0x40014800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;

			clocks = <&rcc STM32_CLOCK(APB1_2, 18U)>;

			resets = <&rctl STM32_RESET(APB1H, 18U)>;

			interrupts = <22 0>;

			interrupt-names = "global";
@@ -295,7 +295,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40005400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;

			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;

			interrupts = <23 0>;

			interrupt-names = "combined";

			status = "disabled";
@@ -304,7 +304,7 @@ 
		adc1: adc@40012400 {

			compatible = "st,stm32-adc";

			reg = <0x40012400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;

			clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;

			interrupts = <12 0>;

			status = "disabled";

			#io-channel-cells = <1>;
@@ -322,7 +322,7 @@ 
			#dma-cells = <3>;

			reg = <0x40020000 0x400>;

			interrupts = <9 0 10 0 10 0>;

			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;

			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;

			dma-requests = <3>;

			dma-offset = <0>;

			status = "disabled";

dts/arm/st/c0/stm32c031.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x50000c00 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;

				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;

			};

		};

	};

dts/arm/st/f0/stm32f0.dtsi

+18 −18
Original line number Diff line number Diff line
@@ -86,7 +86,7 @@ 
			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";

			reg = <0x40022000 0x400>;

			interrupts = <3 0>;

			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;

			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;



			#address-cells = <1>;

			#size-cells = <1>;
@@ -134,7 +134,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x48000000 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;

				clocks = <&rcc STM32_CLOCK(AHB1, 17U)>;

			};



			gpiob: gpio@48000400 {
@@ -142,7 +142,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x48000400 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;

				clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;

			};



			gpioc: gpio@48000800 {
@@ -150,7 +150,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x48000800 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;

				clocks = <&rcc STM32_CLOCK(AHB1, 19U)>;

			};



			gpiod: gpio@48000c00 {
@@ -158,7 +158,7 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x48000c00 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;

				clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;

			};



			gpiof: gpio@48001400 {
@@ -166,14 +166,14 @@ 
				gpio-controller;

				#gpio-cells = <2>;

				reg = <0x48001400 0x400>;

				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;

				clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;

			};

		};



		usart1: serial@40013800 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40013800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;

			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;

			resets = <&rctl STM32_RESET(APB2, 14U)>;

			interrupts = <27 0>;

			status = "disabled";
@@ -185,7 +185,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40005400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,

			clocks = <&rcc STM32_CLOCK(APB1, 21U)>,

				 /* I2C1 clock source should always be defined,

				  * even for the default value

				  */
@@ -200,7 +200,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40013000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;

			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;

			interrupts = <25 3>;

			status = "disabled";

		};
@@ -208,7 +208,7 @@ 
		rtc: rtc@40002800 {

			compatible = "st,stm32-rtc";

			reg = <0x40002800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;

			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;

			interrupts = <2 0>;

			prescaler = <32768>;

			alarms-count = <1>;
@@ -225,7 +225,7 @@ 
		wwdg: watchdog@40002c00 {

			compatible = "st,stm32-window-watchdog";

			reg = <0x40002C00 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;

			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;

			interrupts = <0 2>;

			status = "disabled";

		};
@@ -233,7 +233,7 @@ 
		timers1: timers@40012c00 {

			compatible = "st,stm32-timers";

			reg = <0x40012c00 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;

			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;

			resets = <&rctl STM32_RESET(APB2, 11U)>;

			interrupts = <13 0>, <14 0>;

			interrupt-names = "brk_up_trg_com", "cc";
@@ -250,7 +250,7 @@ 
		timers3: timers@40000400 {

			compatible = "st,stm32-timers";

			reg = <0x40000400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;

			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;

			resets = <&rctl STM32_RESET(APB1, 1U)>;

			interrupts = <16 0>;

			interrupt-names = "global";
@@ -272,7 +272,7 @@ 
		timers14: timers@40002000 {

			compatible = "st,stm32-timers";

			reg = <0x40002000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;

			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;

			resets = <&rctl STM32_RESET(APB1, 8U)>;

			interrupts = <19 0>;

			interrupt-names = "global";
@@ -294,7 +294,7 @@ 
		timers16: timers@40014400 {

			compatible = "st,stm32-timers";

			reg = <0x40014400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;

			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;

			resets = <&rctl STM32_RESET(APB2, 17U)>;

			interrupts = <21 0>;

			interrupt-names = "global";
@@ -316,7 +316,7 @@ 
		timers17: timers@40014800 {

			compatible = "st,stm32-timers";

			reg = <0x40014800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;

			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;

			resets = <&rctl STM32_RESET(APB2, 18U)>;

			interrupts = <22 0>;

			interrupt-names = "global";
@@ -338,7 +338,7 @@ 
		adc1: adc@40012400 {

			compatible = "st,stm32-adc";

			reg = <0x40012400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;

			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;

			interrupts = <12 0>;

			status = "disabled";

			#io-channel-cells = <1>;
@@ -355,7 +355,7 @@ 
			compatible = "st,stm32-dma-v2bis";

			#dma-cells = <2>;

			reg = <0x40020000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;

			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;

			interrupts = <9 0 10 0 10 0 11 0 11 0>;

			status = "disabled";

		};

dts/arm/st/f0/stm32f030X8.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
		usart2: serial@40004400 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40004400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;

			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;

			resets = <&rctl STM32_RESET(APB1, 17U)>;

			interrupts = <28 0>;

			status = "disabled";
@@ -33,7 +33,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40005800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;

			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;

			interrupts = <24 0>;

			interrupt-names = "combined";

			status = "disabled";
@@ -44,7 +44,7 @@ 
			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x40003800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;

			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;

			interrupts = <26 3>;

			status = "disabled";

		};
@@ -52,7 +52,7 @@ 
		timers6: timers@40001000 {

			compatible = "st,stm32-timers";

			reg = <0x40001000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;

			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;

			resets = <&rctl STM32_RESET(APB1, 4U)>;

			interrupts = <17 0>;

			interrupt-names = "global";
@@ -63,7 +63,7 @@ 
		timers15: timers@40014000 {

			compatible = "st,stm32-timers";

			reg = <0x40014000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;

			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;

			resets = <&rctl STM32_RESET(APB2, 16U)>;

			interrupts = <20 0>;

			interrupt-names = "global";

dts/arm/st/f0/stm32f030Xc.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
		usart3: serial@40004800 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40004800 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;

			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;

			resets = <&rctl STM32_RESET(APB1, 18U)>;

			interrupts = <29 0>;

			status = "disabled";
@@ -38,7 +38,7 @@ 
		usart4: serial@40004c00 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40004c00 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;

			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;

			resets = <&rctl STM32_RESET(APB1, 19U)>;

			interrupts = <29 0>;

			status = "disabled";
@@ -47,7 +47,7 @@ 
		usart5: serial@40005000 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40005000 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;

			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;

			resets = <&rctl STM32_RESET(APB1, 20U)>;

			interrupts = <29 0>;

			status = "disabled";
@@ -56,7 +56,7 @@ 
		usart6: serial@40011400 {

			compatible = "st,stm32-usart", "st,stm32-uart";

			reg = <0x40011400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;

			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;

			resets = <&rctl STM32_RESET(APB2, 5U)>;

			interrupts = <29 0>;

			status = "disabled";
@@ -65,7 +65,7 @@ 
		timers7: timers@40001400 {

			compatible = "st,stm32-timers";

			reg = <0x40001400 0x400>;

			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;

			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;

			resets = <&rctl STM32_RESET(APB1, 5U)>;

			interrupts = <18 0>;

			interrupt-names = "global";

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