Commit 5100f118 authored by Sigmund Klåpbakken's avatar Sigmund Klåpbakken Committed by Anas Nashif
Browse files

arch: arm: cortex_a_r: Set XPSR endianness bit 

When this bit is not set, it defaults to 0 (little endian). This
causes issues for big-endian devices, as data will be accessed using
little endian.

Signed-off-by: default avatarSigmund Klåpbakken <sigmundklaa@outlook.com>
parent fb53d2ef

arch/arm/core/cortex_a_r/thread.c

+4 −0
Changes for arch/arm/core/cortex_a_r/thread.c: 4 added lines, 0 removed lines.
Original line number Diff line number Diff line
@@ -95,6 +95,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, 
	iframe->a4 = (uint32_t)p3;



	iframe->xpsr = A_BIT | MODE_SYS;

#if defined(CONFIG_BIG_ENDIAN)

	iframe->xpsr |= E_BIT;

#endif /* CONFIG_BIG_ENDIAN */



#if defined(CONFIG_COMPILER_ISA_THUMB2)

	iframe->xpsr |= T_BIT;

#endif /* CONFIG_COMPILER_ISA_THUMB2 */

include/zephyr/arch/arm/cortex_a_r/cpu.h

+1 −0
Changes for include/zephyr/arch/arm/cortex_a_r/cpu.h: 1 added line, 0 removed lines.
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#define MODE_SYS	0x1f

#define MODE_MASK	0x1f



#define E_BIT	(1 << 9)

#define A_BIT	(1 << 8)

#define I_BIT	(1 << 7)

#define F_BIT	(1 << 6)

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