dts: infineon: Support for PSoC 1M devices (4e5c1dab) · Commits · Wenxi XU / zephyr

dts/arm/infineon/psoc6/mpns/CY8C6016BZI_F04.dtsi

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		/*
		* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
		* an affiliate of Cypress Semiconductor Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv7-m.dtsi>
		#include "../psoc6_01/psoc6_01.124-bga.dtsi"

		&nvic {
		arm,num-irq-priority-bits = <3>;
		};

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Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
		* an affiliate of Cypress Semiconductor Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv7-m.dtsi>
		#include "../psoc6_01/psoc6_01.124-bga.dtsi"

		&nvic {
		arm,num-irq-priority-bits = <3>;
		};

0 → 100644

+13 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
		* an affiliate of Cypress Semiconductor Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv7-m.dtsi>
		#include "../psoc6_01/psoc6_01.124-bga.dtsi"

		&nvic {
		arm,num-irq-priority-bits = <3>;
		};

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+21 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
		* an affiliate of Cypress Semiconductor Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv7-m.dtsi>
		#include "../psoc6_01/psoc6_01.124-bga.dtsi"

		&sram0 {
		reg = <0x8000000 0x48000>;
		};

		&flash0 {
		reg = <0x10000000 0x100000>;
		};

		&nvic {
		arm,num-irq-priority-bits = <3>;
		};

0 → 100644

+21 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
		* an affiliate of Cypress Semiconductor Corporation
		*
		* SPDX-License-Identifier: Apache-2.0
		*/

		#include <arm/armv7-m.dtsi>
		#include "../psoc6_01/psoc6_01.80-wlcsp.dtsi"

		&flash0 {
		reg = <0x10000000 0x100000>;
		};

		&sram0 {
		reg = <0x8000000 0x48000>;
		};

		&nvic {
		arm,num-irq-priority-bits = <3>;
		};