Commit 4df673f3 authored by Yurii Hamann's avatar Yurii Hamann Committed by Kumar Gala
Browse files

drivers: clock_control: STM32F7 family clock control 



This patch adds clock control support for STM32F7 family
microcontrollers.

Signed-off-by: default avatarYurii Hamann <yurii@hamann.site>
parent 7d8d280d

arch/arm/soc/st_stm32/stm32f7/soc.h

+7 −0
Original line number Diff line number Diff line
@@ -23,6 +23,13 @@ 
#include <misc/util.h>

#include <stm32f7xx.h>



#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE

#include <stm32f7xx_ll_utils.h>

#include <stm32f7xx_ll_bus.h>

#include <stm32f7xx_ll_rcc.h>

#include <stm32f7xx_ll_system.h>

#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */



#endif /* !_ASMLANGUAGE */



#endif /* _STM32F7_SOC_H_ */

drivers/clock_control/CMakeLists.txt

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE) 
  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F1X stm32f1x_ll_clock.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X stm32f3x_ll_clock.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X stm32f4x_ll_clock.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X stm32f7x_ll_clock.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X stm32l0x_ll_clock.c)

  zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X stm32l4x_ll_clock.c)

endif()

drivers/clock_control/Kconfig.stm32

+2 −2
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ config CLOCK_STM32_PLL_MULTIPLIER 


endif # SOC_SERIES_STM32F3X



if SOC_SERIES_STM32F4X

if SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X



config CLOCK_STM32_PLL_M_DIVISOR

	int "Division factor for PLL VCO input clock"
@@ -239,7 +239,7 @@ config CLOCK_STM32_PLL_Q_DIVISOR 
	 need a frequency lower than or equal to 48 MHz to work correctly.

	 Allowed values: 2-15



endif # SOC_SERIES_STM32F4X

endif # SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X



if SOC_SERIES_STM32L0X

drivers/clock_control/stm32_ll_clock.c

+10 −4
Original line number Diff line number Diff line
@@ -56,11 +56,14 @@ static inline int stm32_clock_control_on(struct device *dev, 
	case STM32_CLOCK_BUS_AHB1:

		LL_AHB1_GRP1_EnableClock(pclken->enr);

		break;

#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F4X)

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32F4X) || \

	defined(CONFIG_SOC_SERIES_STM32F7X)

	case STM32_CLOCK_BUS_AHB2:

		LL_AHB2_GRP1_EnableClock(pclken->enr);

		break;

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X */

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||

		CONFIG_SOC_SERIES_STM32F7X */

	case STM32_CLOCK_BUS_APB1:

		LL_APB1_GRP1_EnableClock(pclken->enr);

		break;
@@ -96,11 +99,14 @@ static inline int stm32_clock_control_off(struct device *dev, 
	case STM32_CLOCK_BUS_AHB1:

		LL_AHB1_GRP1_DisableClock(pclken->enr);

		break;

#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F4X)

#if defined(CONFIG_SOC_SERIES_STM32L4X) || \

	defined(CONFIG_SOC_SERIES_STM32F4X) || \

	defined(CONFIG_SOC_SERIES_STM32F7X)

	case STM32_CLOCK_BUS_AHB2:

		LL_AHB2_GRP1_DisableClock(pclken->enr);

		break;

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X */

#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||

		CONFIG_SOC_SERIES_STM32F7X */

	case STM32_CLOCK_BUS_APB1:

		LL_APB1_GRP1_DisableClock(pclken->enr);

		break;

drivers/clock_control/stm32f7x_ll_clock.c

0 → 100644
+50 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018 Yurii Hamann

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <soc.h>

#include <soc_registers.h>

#include <clock_control.h>

#include <misc/util.h>

#include <clock_control/stm32_clock_control.h>

#include "stm32_ll_clock.h"





#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL



/* Macros to fill up division factors values */

#define _pllm(v) LL_RCC_PLLM_DIV_ ## v

#define pllm(v) _pllm(v)



#define _pllp(v) LL_RCC_PLLP_DIV_ ## v

#define pllp(v) _pllp(v)



/**

 * @brief fill in pll configuration structure

 */

void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)

{

	pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);

	pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;

	pllinit->PLLP = pllp(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);

}

#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */



/**

 * @brief Activate default clocks

 */

void config_enable_default_clocks(void)

{

	/* Power Interface clock enabled by default */

	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);

}



/**

 * @brief Function kept for driver genericity

 */

void LL_RCC_MSI_Disable(void)

{

	/* Do nothing */

}

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