soc: nxp: MCXW71: Add LPADC node + clocking (4b3d88e8) · Commits · Wenxi XU / zephyr

dts/arm/nxp/nxp_mcxw71.dtsi

+16 −0

Changes for dts/arm/nxp/nxp_mcxw71.dtsi: 16 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -318,6 +318,22 @@
		status = "disabled";
		};

		adc0: adc@47000 {
		compatible = "nxp,lpc-lpadc";
		reg = <0x47000 0x1000>;
		interrupts = <71 0>;
		clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
		voltage-ref= <1>;
		calibration-average = <128>;
		/* pwrlvl 0 is slow speed low power, 1 is opposite */
		power-level = <0>;
		offset-value-a = <0>;
		offset-value-b = <0>;
		#io-channel-cells = <1>;
		nxp,references = <&vref 1800>;
		status = "disabled";
		};

		vref: regulator@4a000 {
		compatible = "nxp,vref";
		regulator-name = "mcxw71-vref";

+6 −0

Changes for soc/nxp/mcx/mcxw/soc.c: 6 added lines, 0 removed lines.
Original line number	Diff line number	Diff line
		@@ -121,6 +121,8 @@ static ALWAYS_INLINE void clock_init(void)
		CLOCK_SetIpSrcDiv(kCLOCK_Lpi2c1, kSCG_SysClkDivBy16);
		CLOCK_SetIpSrc(kCLOCK_Lpspi0, kCLOCK_IpSrcFro192M);
		CLOCK_SetIpSrc(kCLOCK_Lpspi1, kCLOCK_IpSrcFro192M);
		CLOCK_SetIpSrc(kCLOCK_Lpadc0, kCLOCK_IpSrcFro192M);
		CLOCK_SetIpSrcDiv(kCLOCK_Lpadc0, kSCG_SysClkDivBy10);

		/* Ungate clocks if the peripheral is enabled in devicetree */
		if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart0), nxp_lpc_lpuart, okay)) {
		@@ -162,6 +164,10 @@ static ALWAYS_INLINE void clock_init(void)
		if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(vref), nxp_vref, okay)) {
		CLOCK_EnableClock(kCLOCK_Vref0);
		}

		if (DT_NODE_HAS_COMPAT_STATUS(adc0, nxp_lpadc, okay)) {
		CLOCK_EnableClock(kCLOCK_Lpadc0);
		}
		}

		static void vbat_init(void)