Commit 4aae3264 authored by Kumar Gala's avatar Kumar Gala Committed by Kumar Gala
Browse files

dts: arm/arm64: remove DTS 'label' property requirement from gic and timer 

The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property.  Update the dts bindings to not require it and
remove setting of the label property in dts files.

Signed-off-by: default avatarKumar Gala <galak@kernel.org>
parent 416dd6cd

boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts

+0 −3
Changes for boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts: 0 added lines, 3 removed lines.
Original line number Diff line number Diff line
@@ -45,7 +45,6 @@ 
			      IRQ_DEFAULT_PRIORITY>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL

			      IRQ_DEFAULT_PRIORITY>;

		label = "arch_timer";

	};



	uartclk: apb-pclk {
@@ -63,7 +62,6 @@ 
			      <0x2f100000 0x200000>; // GICR

			interrupt-controller;

			#interrupt-cells = <4>;

			label = "GIC";

			status = "okay";

			#address-cells = <1>;

			#size-cells = <1>;
@@ -71,7 +69,6 @@ 
			its: msi-controller@2f020000 {

				compatible = "arm,gic-v3-its";

				reg = <0x2f020000 0x20000>;

				label = "ITS";

				status = "okay";

			};

		};

boards/arm64/xenvm/xenvm.dts

+0 −2
Changes for boards/arm64/xenvm/xenvm.dts: 0 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -54,7 +54,6 @@ 


	gic: interrupt-controller@3001000 {

		compatible = "arm,gic";

		label = "GIC";

		#interrupt-cells = <0x04>;

		#address-cells = <0x00>;

		interrupt-controller;
@@ -67,7 +66,6 @@ 
			      GIC_PPI 0x0e IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY

			      GIC_PPI 0x0b IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;

		interrupt-parent = <&gic>;

		label = "arch_timer";

	};



	hypervisor: hypervisor@38000000 {

dts/arm/broadcom/viper-a72.dtsi

+0 −2
Changes for dts/arm/broadcom/viper-a72.dtsi: 0 added lines, 2 removed lines.
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ 
			      IRQ_DEFAULT_PRIORITY>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL

			      IRQ_DEFAULT_PRIORITY>;

		label = "arch_timer";

	};



	soc {
@@ -42,7 +41,6 @@ 
			      <0x42780000 0x600000>;

			interrupt-controller;

			#interrupt-cells = <4>;

			label = "GIC";

			status = "okay";

		};

	};

dts/arm/intel_socfpga_std/socfpga.dtsi

+0 −1
Changes for dts/arm/intel_socfpga_std/socfpga.dtsi: 0 added lines, 1 removed line.
Original line number Diff line number Diff line
@@ -115,7 +115,6 @@ 
				IRQ_DEFAULT_PRIORITY>;

			 reg = <0xfffec200 0x1C>;

			 clocks = <&osc1>;

			 label = "arch_timer";

		};



		uart0: serial0@ffc02000 {

dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi

+0 −1
Changes for dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi: 0 added lines, 1 removed line.
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ 
			      <0xf1060000 0x20000>;

			interrupt-controller;

			#interrupt-cells = <4>;

			label = "GIC";

			status = "okay";

		};

CRA Git | Maintained and supported by SUSTech CRA and CCSE