Commit 48e0dbbc authored by Dino Li's avatar Dino Li Committed by Anas Nashif
Browse files

soc: it8xxx2: enable CONFIG_RISCV_GP 



This will bring better performance on accessing global variables
that are in 4K span by the GP register.

Signed-off-by: default avatarDino Li <Dino.Li@ite.com.tw>
parent fb18038e

soc/riscv/riscv-ite/common/vector.S

+8 −0
Original line number Diff line number Diff line
@@ -16,6 +16,14 @@ GTEXT(__initialize) 
GTEXT(__irq_wrapper)



SECTION_FUNC(vectors, __start)

#ifdef CONFIG_RISCV_GP

	.option push

	.option norelax

	/* Configure the GP register */

	la gp, __global_pointer$

	.option pop

#endif



	.option norvc;



	/*

soc/riscv/riscv-ite/it8xxx2/Kconfig.defconfig.series

+3 −0
Original line number Diff line number Diff line
@@ -13,6 +13,9 @@ config ITE_IT8XXX2_INTC 
	select FLASH_HAS_DRIVER_ENABLED

	select HAS_FLASH_LOAD_OFFSET



config RISCV_GP

	default y



config SYS_CLOCK_HW_CYCLES_PER_SEC

	default 32768

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