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Commit 460ffe76 authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Anas Nashif
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clock_control: fix to get PLL2 source for PREDV1 working 



Some fixes where needed to get PLL2 source of PREVI1 functional.
Compiled ok with following configuration:
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK=y
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2=0
CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER=8

Jira: ZEP-1758

Change-Id: I5ddfaef1b44c4c4e5e6adedc158a1c9092bc8df5
Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent d17f16d8
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