Commit 427f2c60 authored by Peter Mitsis's avatar Peter Mitsis Committed by Benjamin Cabé
Browse files

kernel: arch: add directed IPIs to x86/intel64

Adds support for directed IPIs to x86/intel64. Use of direct IPIs
can further reduce the number of schedule IPIs sent and processed
in a system. Fewer IPI related ISRs mean that ...
 1. Application code is interrupted less frequently
 2. Lower likelihood of scheduler spinlock contention

Signed-off-by: default avatarPeter Mitsis <peter.mitsis@intel.com>
parent d26396c5
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+1 −0
Changes for arch/x86/Kconfig: 1 added line, 0 removed lines.
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ config X86_64
	select X86_MMX
	select X86_SSE
	select X86_SSE2
	select ARCH_HAS_DIRECTED_IPIS

menu "x86 Features"

+13 −0
Changes for arch/x86/core/intel64/smp.c: 13 added lines, 0 removed lines.
Original line number Diff line number Diff line
@@ -38,3 +38,16 @@ void arch_sched_broadcast_ipi(void)
{
	z_loapic_ipi(0, LOAPIC_ICR_IPI_OTHERS, CONFIG_SCHED_IPI_VECTOR);
}

void arch_sched_directed_ipi(uint32_t cpu_bitmap)
{
	unsigned int num_cpus = arch_num_cpus();

	for (unsigned int i = 0; i < num_cpus; i++) {
		if ((cpu_bitmap & BIT(i)) == 0) {
			continue;
		}

		z_loapic_ipi(i, LOAPIC_ICR_IPI_SPECIFIC, CONFIG_SCHED_IPI_VECTOR);
	}
}
+1 −0
Changes for include/zephyr/drivers/interrupt_controller/loapic.h: 1 added line, 0 removed lines.
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@

#define LOAPIC_ICR_BUSY		0x00001000	/* delivery status: 1 = busy */

#define LOAPIC_ICR_IPI_SPECIFIC 0x00004000U     /* target IPI to specific CPU */
#define LOAPIC_ICR_IPI_OTHERS	0x000C4000U	/* normal IPI to other CPUs */
#define LOAPIC_ICR_IPI_INIT	0x00004500U
#define LOAPIC_ICR_IPI_STARTUP	0x00004600U