Commit 41e140d7 authored by Quy Tran's avatar Quy Tran Committed by Anas Nashif
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soc: renesas: Add initial support for RA4M3 SOC 



Initial commit to support Renesas RA4M3 SOC

Signed-off-by: default avatarQuy Tran <quy.tran.pz@renesas.com>
parent 7638952f

dts/arm/renesas/ra/ra4/r7fa4m3af3cfb.dtsi

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/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <zephyr/dt-bindings/clock/ra_clock.h>

#include <arm/renesas/ra/ra4/r7fa4m3ax.dtsi>



/ {

	soc {

		flash-controller@407e0000 {

			reg = <0x407e0000 0x1000>;

			#address-cells = <1>;

			#size-cells = <1>;

			flash0: flash@0 {

				compatible = "soc-nv-flash";

				reg = <0x0 DT_SIZE_M(1)>;

			};

		};

	};

};

dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi

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/*

 * Copyright (c) 2024 Renesas Electronics Corporation

 *

 * SPDX-License-Identifier: Apache-2.0

 */



#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>

#include <zephyr/dt-bindings/clock/ra_clock.h>



/ {

	soc {

		sram0: memory@20000000 {

			compatible = "mmio-sram";

			reg = <0x20000000 DT_SIZE_K(128)>;

		};



		ioport6: gpio@400800c0 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x400800c0 0x20>;

			port = <6>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport7: gpio@400800e0 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x400800e0 0x20>;

			port = <7>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		ioport8: gpio@40080100 {

			compatible = "renesas,ra-gpio-ioport";

			reg = <0x40080100 0x20>;

			port = <8>;

			gpio-controller;

			#gpio-cells = <2>;

			ngpios = <16>;

			status = "disabled";

		};



		sci1: sci1@40118100 {

			compatible = "renesas,ra-sci";

			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40118100 0x100>;

			clocks = <&pclka MSTPB 30>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <1>;

				status = "disabled";

			};

		};



		sci2: sci2@40118200 {

			compatible = "renesas,ra-sci";

			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40118200 0x100>;

			clocks = <&pclka MSTPB 29>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <2>;

				status = "disabled";

			};

		};



		sci3: sci3@40118300 {

			compatible = "renesas,ra-sci";

			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40118300 0x100>;

			clocks = <&pclka MSTPB 28>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <3>;

				status = "disabled";

			};

		};



		sci4: sci4@40118400 {

			compatible = "renesas,ra-sci";

			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;

			interrupt-names = "rxi", "txi", "tei", "eri";

			reg = <0x40118400 0x100>;

			clocks = <&pclka MSTPB 27>;

			status = "disabled";

			uart {

				compatible = "renesas,ra-sci-uart";

				channel = <4>;

				status = "disabled";

			};

		};

	};



    clocks: clocks {

		xtal: clock-xtal {

			compatible = "renesas,ra-cgc-external-clock";

			clock-frequency = <DT_FREQ_M(24)>;

			#clock-cells = <0>;

			status = "disabled";

		};



		hoco: clock-hoco {

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_M(20)>;

			#clock-cells = <0>;

		};



		moco: clock-moco {

			compatible = "fixed-clock";

			clock-frequency = <DT_FREQ_M(8)>;

			#clock-cells = <0>;

		};



		loco: clock-loco {

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			#clock-cells = <0>;

		};



		subclk: clock-subclk {

			compatible = "renesas,ra-cgc-subclk";

			clock-frequency = <32768>;

			#clock-cells = <0>;

			status = "disabled";

		};



		pll: pll {

			compatible = "renesas,ra-cgc-pll";

			#clock-cells = <0>;



			/* PLL */

			source = <RA_PLL_SOURCE_MAIN_OSC>;

			div = <RA_PLL_DIV_3>;

			mul = <25 0>;

			status = "disabled";

			freq = <DT_FREQ_M(200)>;

		};



		pll2: pll2 {

			compatible = "renesas,ra-cgc-pll";

			#clock-cells = <0>;

			source = <RA_PLL_SOURCE_DISABLE>;

			div = <RA_PLL_DIV_2>;

			mul = <20 0>;

			status = "disabled";

		};



		pclkblock: pclkblock {

			compatible = "renesas,ra-cgc-pclk-block";

			#clock-cells = <0>;

			sysclock-src = <RA_CLOCK_SOURCE_PLL>;

			status = "okay";



			iclk: iclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclka: pclka {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkb: pclkb {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_4>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkc: pclkc {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_4>;

				#clock-cells = <2>;

				status = "okay";

			};



			pclkd: pclkd {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_2>;

				#clock-cells = <2>;

				status = "okay";

			};



			fclk: fclk {

				compatible = "renesas,ra-cgc-pclk";

				clk_div = <RA_SYS_CLOCK_DIV_4>;

				#clock-cells = <2>;

				status = "okay";

			};



			clkout: clkout {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};



			uclk: uclk {

				compatible = "renesas,ra-cgc-pclk";

				#clock-cells = <2>;

				status = "disabled";

			};

		};

	};

};

soc/renesas/ra/ra4m3/CMakeLists.txt

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# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



zephyr_include_directories(.)



zephyr_sources(

  soc.c

)



zephyr_linker_sources(SECTIONS sections.ld)



set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4m3/Kconfig

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# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



config SOC_SERIES_RA4M3

	select ARM

	select CPU_HAS_ARM_MPU

	select CPU_CORTEX_M33

	select HAS_RENESAS_RA_FSP

	select CPU_CORTEX_M_HAS_DWT

	select ARMV8_M_DSP

	select CPU_HAS_FPU

	select FPU

	select HAS_SWO

	select XIP

soc/renesas/ra/ra4m3/Kconfig.defconfig

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# Copyright (c) 2024 Renesas Electronics Corporation

# SPDX-License-Identifier: Apache-2.0



if SOC_SERIES_RA4M3



config NUM_IRQS

	default 96



config PINCTRL

	default y



endif # SOC_SERIES_RA4M3

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