Commit 3ae9a358 authored by Tim Lin's avatar Tim Lin Committed by Carles Cufi
Browse files

ITE: drivers/i2c/target: Disable the timeout setting 



Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.

Signed-off-by: default avatarTim Lin <tim2.lin@ite.corp-partner.google.com>
parent 5de9203a

drivers/i2c/i2c_ite_enhance.c

+3 −5
Original line number Diff line number Diff line
@@ -1222,11 +1222,9 @@ static int i2c_enhance_target_register(const struct device *dev, 
	/* Software reset */

	IT8XXX2_I2C_DHTR(base) |= IT8XXX2_I2C_SOFT_RST;

	IT8XXX2_I2C_DHTR(base) &= ~IT8XXX2_I2C_SOFT_RST;

	/*

	 * Set time out register.

	 * I2C D/E/F clock/data low timeout.

	 */

	IT8XXX2_I2C_TOR(base) = I2C_CLK_LOW_TIMEOUT;

	/* Disable the timeout setting when clock/data are in a low state */

	IT8XXX2_I2C_TO_ARB_ST(base) &= ~(IT8XXX2_I2C_SCL_TIMEOUT_EN |

					 IT8XXX2_I2C_SDA_TIMEOUT_EN);

	/* Bit stretching */

	IT8XXX2_I2C_TOS(base) |= IT8XXX2_I2C_CLK_STRETCH;

	/* Peripheral address(8-bit) */

soc/riscv/riscv-ite/common/chip_chipregs.h

+3 −0
Original line number Diff line number Diff line
@@ -1347,6 +1347,9 @@ enum chip_pll_mode { 
/* 0x13: Nack Status */

#define IT8XXX2_I2C_NST_CNS           BIT(7)

#define IT8XXX2_I2C_NST_ID_NACK       BIT(3)

/* 0x18: Timeout and Arbiter Status */

#define IT8XXX2_I2C_SCL_TIMEOUT_EN    BIT(7)

#define IT8XXX2_I2C_SDA_TIMEOUT_EN    BIT(6)

/* 0x19: Error Status */

#define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ  BIT(0)

/* 0x1B: Finish Status */

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