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Commit 30e662d1 authored by Teik Heng Chong's avatar Teik Heng Chong Committed by Fabio Baltieri
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dts: bindings: clock: Add clock binding file for Intel Agilex Soc FPGA 



Fix the missing Intel Agilex clock manager binding file

Signed-off-by: default avatarTeik Heng Chong <teik.heng.chong@intel.com>
parent 6cd35242
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