Commit 2f864d54 authored by Sanjay Vallimanalan's avatar Sanjay Vallimanalan Committed by Benjamin Cabé
Browse files

dts: arm/ti/mspm0: add cpu power states for MSPM0 series 



add range of cpu power states (run/sleep, stop and standby) for MSPM0
series. add exit latencies ranging from 1.5-15.7µs and minimum
residency times of 5-10ms for optimal power management transitions.

Signed-off-by: default avatarSanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: default avatarParthiban Nallathambi <parthiban@linumiz.com>
parent 35c485b6

dts/arm/ti/mspm0/g/mspm0g.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -155,3 +155,38 @@ 
		};

	};

};



&run1 {

	exit-latency-us = <2>; /* 1.5us */

	min-residency-us = <5000>;

};



&run2 {

	exit-latency-us = <3>; /* 2.1us */

	min-residency-us = <5000>;

};



&stop0 {

	exit-latency-us = <13>; /* 12.1us */

	min-residency-us = <7500>;

};



&stop1 {

	exit-latency-us = <14>; /* 13.5us */

	min-residency-us = <7500>;

};



&stop2 {

	exit-latency-us = <13>; /* 12.9us */

	min-residency-us = <7500>;

};



&stdby0 {

	exit-latency-us = <16>; /* 15.2us */

	min-residency-us = <10000>;

};



&stdby1 {

	exit-latency-us = <16>; /* 15.2us */

	min-residency-us = <10000>;

};

dts/arm/ti/mspm0/l/mspm0l.dtsi

+40 −0
Original line number Diff line number Diff line
@@ -17,3 +17,43 @@ 
		#gpio-cells = <2>;

	};

};



&run0 {

	exit-latency-us = <2>; /* 1.5us */

	min-residency-us = <5000>;

};



&run1 {

	exit-latency-us = <3>; /* 2.1us */

	min-residency-us = <5000>;

};



&run2 {

	exit-latency-us = <3>; /* 2.5us */

	min-residency-us = <5000>;

};



&stop0 {

	exit-latency-us = <13>; /* 12.5us */

	min-residency-us = <7500>;

};



&stop1 {

	exit-latency-us = <15>; /* 14.6us */

	min-residency-us = <7500>;

};



&stop2 {

	exit-latency-us = <14>; /* 13.5us */

	min-residency-us = <7500>;

};



&stdby0 {

	exit-latency-us = <16>; /* 15.7us */

	min-residency-us = <10000>;

};



&stdby1 {

	exit-latency-us = <16>; /* 15.7us */

	min-residency-us = <10000>;

};

dts/arm/ti/mspm0/mspm0.dtsi

+53 −0
Original line number Diff line number Diff line
@@ -20,6 +20,59 @@ 
			reg = <0>;

			#address-cells = <1>;

			#size-cells = <1>;

			cpu-power-states = <&run0 &run1 &run2

					    &stop0 &stop1 &stop2

					    &stdby0 &stdby1>;

		};



		power-states {

			run0: runsleep0 {

				compatible = "zephyr,power-state";

				power-state-name = "runtime-idle";

				substate-id = <1>;

			};



			run1: runsleep1 {

				compatible = "zephyr,power-state";

				power-state-name = "runtime-idle";

				substate-id = <2>;

			};



			run2: runsleep2 {

				compatible = "zephyr,power-state";

				power-state-name = "runtime-idle";

				substate-id = <3>;

			};



			stop0: stop0 {

				compatible = "zephyr,power-state";

				power-state-name = "suspend-to-idle";

				substate-id = <1>;

			};



			stop1: stop1 {

				compatible = "zephyr,power-state";

				power-state-name = "suspend-to-idle";

				substate-id = <2>;

			};



			stop2: stop2 {

				compatible = "zephyr,power-state";

				power-state-name = "suspend-to-idle";

				substate-id = <3>;

			};



			stdby0: standby0 {

				compatible = "zephyr,power-state";

				power-state-name = "standby";

				substate-id = <1>;

			};



			stdby1: standby1 {

				compatible = "zephyr,power-state";

				power-state-name = "standby";

				substate-id = <2>;

			};

		};

	};

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