dts: arm64: nxp: add LPI2C DT nodes for imx91 (2efe6ab3) · Commits · Wenxi XU / zephyr

dts/arm64/nxp/nxp_mimx91.dtsi

+97 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@
		#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
		#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
		#include <zephyr/dt-bindings/gpio/gpio.h>
		#include <zephyr/dt-bindings/i2c/i2c.h>

		/ {
		#address-cells = <1>;
		@@ -141,6 +142,102 @@
		clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>;
		status = "disabled";
		};

		lpi2c1: i2c@44340000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x44340000 0x4000>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>;
		status = "disabled";
		};

		lpi2c2: i2c@44350000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x44350000 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>;
		status = "disabled";
		};

		lpi2c3: i2c@42530000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x42530000 0x4000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>;
		status = "disabled";
		};

		lpi2c4: i2c@42540000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x42540000 0x4000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>;
		status = "disabled";
		};

		lpi2c5: i2c@426b0000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x426b0000 0x4000>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>;
		status = "disabled";
		};

		lpi2c6: i2c@426c0000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x426c0000 0x4000>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>;
		status = "disabled";
		};

		lpi2c7: i2c@426d0000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x426d0000 0x4000>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C7_CLK 0x80 24>;
		status = "disabled";
		};

		lpi2c8: i2c@426e0000 {
		compatible = "nxp,lpi2c";
		clock-frequency = <I2C_BITRATE_STANDARD>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x426e0000 0x4000>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
		clocks = <&ccm IMX_CCM_LPI2C8_CLK 0x80 24>;
		status = "disabled";
		};
		};

		&gpio1{

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