Commit 2cb6e1ee authored by Arunprasath P's avatar Arunprasath P Committed by Anas Nashif
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dts: arm: microchip: add dtsi files for Microchip PIC32CM JH SoC series



Adds common and SoC-specific .dtsi files for the Microchip
PIC32CM JH family. These files define core peripherals,
address maps, and interrupt controller structure shared
across the PIC32CM JH variants.

Signed-off-by: default avatarArunprasath P <arunprasath.p@microchip.com>
parent 7559dd87
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/*
 * Copyright (c) 2025 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Memory configuration: Flash size, RAM Size and Data Flash size for 1216 devices */

/ {
	soc {
		flash0: flash@0 {
			reg = <0x0 DT_SIZE_K(128)>;
		};

		sram0: memory@20000000 {
			reg = <0x20000000 DT_SIZE_K(16)>;
		};
	};
};
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/*
 * Copyright (c) 2025 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Memory configuration: Flash size, RAM Size, Data Flash size
 * and additional nodes for 2532 memory variants
 */

/ {
	soc {
		flash0: flash@0 {
			reg = <0x0 DT_SIZE_K(256)>;
		};

		sram0: memory@20000000 {
			reg = <0x20000000 DT_SIZE_K(32)>;
		};
	};
};
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/*
 * Copyright (c) 2025 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Memory configuration: Flash size, RAM Size, Data Flash size
 * and additional nodes for 5164 memory variants
 */

/ {
	soc {
		flash0: flash@0 {
			reg = <0x0 DT_SIZE_K(512)>;
		};

		sram0: memory@20000000 {
			reg = <0x20000000 DT_SIZE_K(64)>;
		};
	};
};
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/*
 * Copyright (c) 2025 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Common SoC definitions shared across all PIC32CM JH devices */

#include <arm/armv6-m.dtsi>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m0+";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv6m-mpu";
				reg = <0xe000ed90 0x2c>;
			};
		};
	};

	soc {
		flash0: flash@0 {
			compatible = "soc-nv-flash";
			write-block-size = <4>;
		};

		sram0: memory@20000000 {
			compatible = "mmio-sram";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <2>;
};
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/*
 * Copyright (c) 2025 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Device-tree nodes specific to 100-pin package variants */

#include <microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi>
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